Wala shell

Advanced PHP File Manager

Server IP: 127.0.0.1 | PHP Version: 8.3.30 | Domains Hosted: 54

Name	Size	Last Modified
📁 ..	-	2026-03-31 19:08
📄 bnxt_re-abi.h /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) / / * Broadcom NetXtreme-E RoCE driver. * * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term * Broadcom refers to Broadcom Limited and/or its subsidiaries. * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU * General Public License (GPL) Version 2, available from the file * COPYING in the main directory of this source tree, or the * BSD license below: * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Description: Uverbs ABI header file / #ifndef __BNXT_RE_UVERBS_ABI_H__ #define __BNXT_RE_UVERBS_ABI_H__ #include <linux/types.h> #include <rdma/ib_user_ioctl_cmds.h> #define BNXT_RE_ABI_VERSION 1 #define BNXT_RE_CHIP_ID0_CHIP_NUM_SFT 0x00 #define BNXT_RE_CHIP_ID0_CHIP_REV_SFT 0x10 #define BNXT_RE_CHIP_ID0_CHIP_MET_SFT 0x18 enum { BNXT_RE_UCNTX_CMASK_HAVE_CCTX = 0x1ULL, BNXT_RE_UCNTX_CMASK_HAVE_MODE = 0x02ULL, BNXT_RE_UCNTX_CMASK_WC_DPI_ENABLED = 0x04ULL, BNXT_RE_UCNTX_CMASK_DBR_PACING_ENABLED = 0x08ULL, BNXT_RE_UCNTX_CMASK_POW2_DISABLED = 0x10ULL, BNXT_RE_UCNTX_CMASK_MSN_TABLE_ENABLED = 0x40, }; enum bnxt_re_wqe_mode { BNXT_QPLIB_WQE_MODE_STATIC = 0x00, BNXT_QPLIB_WQE_MODE_VARIABLE = 0x01, BNXT_QPLIB_WQE_MODE_INVALID = 0x02, }; enum { BNXT_RE_COMP_MASK_REQ_UCNTX_POW2_SUPPORT = 0x01, BNXT_RE_COMP_MASK_REQ_UCNTX_VAR_WQE_SUPPORT = 0x02, }; struct bnxt_re_uctx_req { __aligned_u64 comp_mask; }; struct bnxt_re_uctx_resp { __u32 dev_id; __u32 max_qp; __u32 pg_size; __u32 cqe_sz; __u32 max_cqd; __u32 rsvd; __aligned_u64 comp_mask; __u32 chip_id0; __u32 chip_id1; __u32 mode; __u32 rsvd1; / padding / }; / * This struct is placed after the ib_uverbs_alloc_pd_resp struct, which is * not 8 byted aligned. To avoid undesired padding in various cases we have to * set this struct to packed. / struct bnxt_re_pd_resp { __u32 pdid; __u32 dpi; __u64 dbr; } __attribute__((packed, aligned(4))); struct bnxt_re_cq_req { __aligned_u64 cq_va; __aligned_u64 cq_handle; }; enum bnxt_re_cq_mask { BNXT_RE_CQ_TOGGLE_PAGE_SUPPORT = 0x1, }; struct bnxt_re_cq_resp { __u32 cqid; __u32 tail; __u32 phase; __u32 rsvd; __aligned_u64 comp_mask; }; struct bnxt_re_resize_cq_req { __aligned_u64 cq_va; }; enum bnxt_re_qp_mask { BNXT_RE_QP_REQ_MASK_VAR_WQE_SQ_SLOTS = 0x1, }; struct bnxt_re_qp_req { __aligned_u64 qpsva; __aligned_u64 qprva; __aligned_u64 qp_handle; __aligned_u64 comp_mask; __u32 sq_slots; }; struct bnxt_re_qp_resp { __u32 qpid; __u32 rsvd; }; struct bnxt_re_srq_req { __aligned_u64 srqva; __aligned_u64 srq_handle; }; enum bnxt_re_srq_mask { BNXT_RE_SRQ_TOGGLE_PAGE_SUPPORT = 0x1, }; struct bnxt_re_srq_resp { __u32 srqid; __u32 rsvd; / padding / __aligned_u64 comp_mask; }; enum bnxt_re_shpg_offt { BNXT_RE_BEG_RESV_OFFT = 0x00, BNXT_RE_AVID_OFFT = 0x10, BNXT_RE_AVID_SIZE = 0x04, BNXT_RE_END_RESV_OFFT = 0xFF0 }; enum bnxt_re_objects { BNXT_RE_OBJECT_ALLOC_PAGE = (1U << UVERBS_ID_NS_SHIFT), BNXT_RE_OBJECT_NOTIFY_DRV, BNXT_RE_OBJECT_GET_TOGGLE_MEM, }; enum bnxt_re_alloc_page_type { BNXT_RE_ALLOC_WC_PAGE = 0, BNXT_RE_ALLOC_DBR_BAR_PAGE, BNXT_RE_ALLOC_DBR_PAGE, }; enum bnxt_re_var_alloc_page_attrs { BNXT_RE_ALLOC_PAGE_HANDLE = (1U << UVERBS_ID_NS_SHIFT), BNXT_RE_ALLOC_PAGE_TYPE, BNXT_RE_ALLOC_PAGE_DPI, BNXT_RE_ALLOC_PAGE_MMAP_OFFSET, BNXT_RE_ALLOC_PAGE_MMAP_LENGTH, }; enum bnxt_re_alloc_page_attrs { BNXT_RE_DESTROY_PAGE_HANDLE = (1U << UVERBS_ID_NS_SHIFT), }; enum bnxt_re_alloc_page_methods { BNXT_RE_METHOD_ALLOC_PAGE = (1U << UVERBS_ID_NS_SHIFT), BNXT_RE_METHOD_DESTROY_PAGE, }; enum bnxt_re_notify_drv_methods { BNXT_RE_METHOD_NOTIFY_DRV = (1U << UVERBS_ID_NS_SHIFT), }; / Toggle mem / enum bnxt_re_get_toggle_mem_type { BNXT_RE_CQ_TOGGLE_MEM = 0, BNXT_RE_SRQ_TOGGLE_MEM, }; enum bnxt_re_var_toggle_mem_attrs { BNXT_RE_TOGGLE_MEM_HANDLE = (1U << UVERBS_ID_NS_SHIFT), BNXT_RE_TOGGLE_MEM_TYPE, BNXT_RE_TOGGLE_MEM_RES_ID, BNXT_RE_TOGGLE_MEM_MMAP_PAGE, BNXT_RE_TOGGLE_MEM_MMAP_OFFSET, BNXT_RE_TOGGLE_MEM_MMAP_LENGTH, }; enum bnxt_re_toggle_mem_attrs { BNXT_RE_RELEASE_TOGGLE_MEM_HANDLE = (1U << UVERBS_ID_NS_SHIFT), }; enum bnxt_re_toggle_mem_methods { BNXT_RE_METHOD_GET_TOGGLE_MEM = (1U << UVERBS_ID_NS_SHIFT), BNXT_RE_METHOD_RELEASE_TOGGLE_MEM, }; #endif / __BNXT_RE_UVERBS_ABI_H__*/	5.55 KB	2026-03-24 10:01
📄 cxgb4-abi.h /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) / / * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved. * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU * General Public License (GPL) Version 2, available from the file * COPYING in the main directory of this source tree, or the * OpenIB.org BSD license below: * * Redistribution and use in source and binary forms, with or * without modification, are permitted provided that the following * conditions are met: * * - Redistributions of source code must retain the above * copyright notice, this list of conditions and the following * disclaimer. * * - Redistributions in binary form must reproduce the above * copyright notice, this list of conditions and the following * disclaimer in the documentation and/or other materials * provided with the distribution. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. / #ifndef CXGB4_ABI_USER_H #define CXGB4_ABI_USER_H #include <linux/types.h> #define C4IW_UVERBS_ABI_VERSION 3 / * Make sure that all structs defined in this file remain laid out so * that they pack the same way on 32-bit and 64-bit architectures (to * avoid incompatibility between 32-bit userspace and 64-bit kernels). * In particular do not use pointer types -- pass pointers in __aligned_u64 * instead. / enum { C4IW_64B_CQE = (1 << 0) }; struct c4iw_create_cq { __u32 flags; __u32 reserved; }; struct c4iw_create_cq_resp { __aligned_u64 key; __aligned_u64 gts_key; __aligned_u64 memsize; __u32 cqid; __u32 size; __u32 qid_mask; __u32 flags; }; enum { C4IW_QPF_ONCHIP = (1 << 0), C4IW_QPF_WRITE_W_IMM = (1 << 1) }; struct c4iw_create_qp_resp { __aligned_u64 ma_sync_key; __aligned_u64 sq_key; __aligned_u64 rq_key; __aligned_u64 sq_db_gts_key; __aligned_u64 rq_db_gts_key; __aligned_u64 sq_memsize; __aligned_u64 rq_memsize; __u32 sqid; __u32 rqid; __u32 sq_size; __u32 rq_size; __u32 qid_mask; __u32 flags; }; struct c4iw_create_srq_resp { __aligned_u64 srq_key; __aligned_u64 srq_db_gts_key; __aligned_u64 srq_memsize; __u32 srqid; __u32 srq_size; __u32 rqt_abs_idx; __u32 qid_mask; __u32 flags; __u32 reserved; / explicit padding / }; enum { / HW supports SRQ_LIMIT_REACHED event / T4_SRQ_LIMIT_SUPPORT = 1 << 0, }; struct c4iw_alloc_ucontext_resp { __aligned_u64 status_page_key; __u32 status_page_size; __u32 reserved; / explicit padding (optional for i386) / }; struct c4iw_alloc_pd_resp { __u32 pdid; }; #endif / CXGB4_ABI_USER_H */	3.05 KB	2026-03-24 10:01
📄 efa-abi.h /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) / / * Copyright 2018-2024 Amazon.com, Inc. or its affiliates. All rights reserved. / #ifndef EFA_ABI_USER_H #define EFA_ABI_USER_H #include <linux/types.h> #include <rdma/ib_user_ioctl_cmds.h> / * Increment this value if any changes that break userspace ABI * compatibility are made. / #define EFA_UVERBS_ABI_VERSION 1 / * Keep structs aligned to 8 bytes. * Keep reserved fields as arrays of __u8 named reserved_XXX where XXX is the * hex bit offset of the field. / enum { EFA_ALLOC_UCONTEXT_CMD_COMP_TX_BATCH = 1 << 0, EFA_ALLOC_UCONTEXT_CMD_COMP_MIN_SQ_WR = 1 << 1, }; struct efa_ibv_alloc_ucontext_cmd { __u32 comp_mask; __u8 reserved_20[4]; }; enum efa_ibv_user_cmds_supp_udata { EFA_USER_CMDS_SUPP_UDATA_QUERY_DEVICE = 1 << 0, EFA_USER_CMDS_SUPP_UDATA_CREATE_AH = 1 << 1, }; struct efa_ibv_alloc_ucontext_resp { __u32 comp_mask; __u32 cmds_supp_udata_mask; __u16 sub_cqs_per_cq; __u16 inline_buf_size; __u32 max_llq_size; / bytes / __u16 max_tx_batch; / units of 64 bytes / __u16 min_sq_wr; __u8 reserved_a0[4]; }; struct efa_ibv_alloc_pd_resp { __u32 comp_mask; __u16 pdn; __u8 reserved_30[2]; }; enum { EFA_CREATE_CQ_WITH_COMPLETION_CHANNEL = 1 << 0, EFA_CREATE_CQ_WITH_SGID = 1 << 1, }; struct efa_ibv_create_cq { __u32 comp_mask; __u32 cq_entry_size; __u16 num_sub_cqs; __u8 flags; __u8 reserved_58[5]; }; enum { EFA_CREATE_CQ_RESP_DB_OFF = 1 << 0, }; struct efa_ibv_create_cq_resp { __u32 comp_mask; __u8 reserved_20[4]; __aligned_u64 q_mmap_key; __aligned_u64 q_mmap_size; __u16 cq_idx; __u8 reserved_d0[2]; __u32 db_off; __aligned_u64 db_mmap_key; }; enum { EFA_QP_DRIVER_TYPE_SRD = 0, }; enum { EFA_CREATE_QP_WITH_UNSOLICITED_WRITE_RECV = 1 << 0, }; struct efa_ibv_create_qp { __u32 comp_mask; __u32 rq_ring_size; / bytes / __u32 sq_ring_size; / bytes / __u32 driver_qp_type; __u16 flags; __u8 sl; __u8 reserved_98[5]; }; struct efa_ibv_create_qp_resp { __u32 comp_mask; / the offset inside the page of the rq db / __u32 rq_db_offset; / the offset inside the page of the sq db / __u32 sq_db_offset; / the offset inside the page of descriptors buffer / __u32 llq_desc_offset; __aligned_u64 rq_mmap_key; __aligned_u64 rq_mmap_size; __aligned_u64 rq_db_mmap_key; __aligned_u64 sq_db_mmap_key; __aligned_u64 llq_desc_mmap_key; __u16 send_sub_cq_idx; __u16 recv_sub_cq_idx; __u8 reserved_1e0[4]; }; struct efa_ibv_create_ah_resp { __u32 comp_mask; __u16 efa_address_handle; __u8 reserved_30[2]; }; enum { EFA_QUERY_DEVICE_CAPS_RDMA_READ = 1 << 0, EFA_QUERY_DEVICE_CAPS_RNR_RETRY = 1 << 1, EFA_QUERY_DEVICE_CAPS_CQ_NOTIFICATIONS = 1 << 2, EFA_QUERY_DEVICE_CAPS_CQ_WITH_SGID = 1 << 3, EFA_QUERY_DEVICE_CAPS_DATA_POLLING_128 = 1 << 4, EFA_QUERY_DEVICE_CAPS_RDMA_WRITE = 1 << 5, EFA_QUERY_DEVICE_CAPS_UNSOLICITED_WRITE_RECV = 1 << 6, }; struct efa_ibv_ex_query_device_resp { __u32 comp_mask; __u32 max_sq_wr; __u32 max_rq_wr; __u16 max_sq_sge; __u16 max_rq_sge; __u32 max_rdma_size; __u32 device_caps; }; enum { EFA_QUERY_MR_VALIDITY_RECV_IC_ID = 1 << 0, EFA_QUERY_MR_VALIDITY_RDMA_READ_IC_ID = 1 << 1, EFA_QUERY_MR_VALIDITY_RDMA_RECV_IC_ID = 1 << 2, }; enum efa_query_mr_attrs { EFA_IB_ATTR_QUERY_MR_HANDLE = (1U << UVERBS_ID_NS_SHIFT), EFA_IB_ATTR_QUERY_MR_RESP_IC_ID_VALIDITY, EFA_IB_ATTR_QUERY_MR_RESP_RECV_IC_ID, EFA_IB_ATTR_QUERY_MR_RESP_RDMA_READ_IC_ID, EFA_IB_ATTR_QUERY_MR_RESP_RDMA_RECV_IC_ID, }; enum efa_mr_methods { EFA_IB_METHOD_MR_QUERY = (1U << UVERBS_ID_NS_SHIFT), }; #endif / EFA_ABI_USER_H */	3.57 KB	2026-03-24 10:01
📁 hfi	-	2026-03-27 02:43
📄 hns-abi.h /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) / / * Copyright (c) 2016 Hisilicon Limited. * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU * General Public License (GPL) Version 2, available from the file * COPYING in the main directory of this source tree, or the * OpenIB.org BSD license below: * * Redistribution and use in source and binary forms, with or * without modification, are permitted provided that the following * conditions are met: * * - Redistributions of source code must retain the above * copyright notice, this list of conditions and the following * disclaimer. * * - Redistributions in binary form must reproduce the above * copyright notice, this list of conditions and the following * disclaimer in the documentation and/or other materials * provided with the distribution. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. / #ifndef HNS_ABI_USER_H #define HNS_ABI_USER_H #include <linux/types.h> struct hns_roce_ib_create_cq { __aligned_u64 buf_addr; __aligned_u64 db_addr; __u32 cqe_size; __u32 reserved; }; enum hns_roce_cq_cap_flags { HNS_ROCE_CQ_FLAG_RECORD_DB = 1 << 0, }; struct hns_roce_ib_create_cq_resp { __aligned_u64 cqn; / Only 32 bits used, 64 for compat / __aligned_u64 cap_flags; }; struct hns_roce_ib_create_srq { __aligned_u64 buf_addr; __aligned_u64 db_addr; __aligned_u64 que_addr; }; struct hns_roce_ib_create_srq_resp { __u32 srqn; __u32 reserved; }; struct hns_roce_ib_create_qp { __aligned_u64 buf_addr; __aligned_u64 db_addr; __u8 log_sq_bb_count; __u8 log_sq_stride; __u8 sq_no_prefetch; __u8 reserved[5]; __aligned_u64 sdb_addr; }; enum hns_roce_qp_cap_flags { HNS_ROCE_QP_CAP_RQ_RECORD_DB = 1 << 0, HNS_ROCE_QP_CAP_SQ_RECORD_DB = 1 << 1, HNS_ROCE_QP_CAP_OWNER_DB = 1 << 2, }; struct hns_roce_ib_create_qp_resp { __aligned_u64 cap_flags; }; struct hns_roce_ib_alloc_ucontext_resp { __u32 qp_tab_size; __u32 cqe_size; __u32 srq_tab_size; __u32 reserved; }; struct hns_roce_ib_alloc_pd_resp { __u32 pdn; }; #endif / HNS_ABI_USER_H */	2.62 KB	2026-03-24 10:01
📄 ib_user_ioctl_cmds.h /* * Copyright (c) 2018, Mellanox Technologies inc. All rights reserved. * Copyright (c) 2020, Intel Corporation. All rights reserved. * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU * General Public License (GPL) Version 2, available from the file * COPYING in the main directory of this source tree, or the * OpenIB.org BSD license below: * * Redistribution and use in source and binary forms, with or * without modification, are permitted provided that the following * conditions are met: * * - Redistributions of source code must retain the above * copyright notice, this list of conditions and the following * disclaimer. * * - Redistributions in binary form must reproduce the above * copyright notice, this list of conditions and the following * disclaimer in the documentation and/or other materials * provided with the distribution. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. / #ifndef IB_USER_IOCTL_CMDS_H #define IB_USER_IOCTL_CMDS_H #define UVERBS_ID_NS_MASK 0xF000 #define UVERBS_ID_NS_SHIFT 12 enum uverbs_default_objects { UVERBS_OBJECT_DEVICE, / No instances of DEVICE are allowed */ UVERBS_OBJECT_PD, UVERBS_OBJECT_COMP_CHANNEL, UVERBS_OBJECT_CQ, UVERBS_OBJECT_QP, UVERBS_OBJECT_SRQ, UVERBS_OBJECT_AH, UVERBS_OBJECT_MR, UVERBS_OBJECT_MW, UVERBS_OBJECT_FLOW, UVERBS_OBJECT_XRCD, UVERBS_OBJECT_RWQ_IND_TBL, UVERBS_OBJECT_WQ, UVERBS_OBJECT_FLOW_ACTION, UVERBS_OBJECT_DM, UVERBS_OBJECT_COUNTERS, UVERBS_OBJECT_ASYNC_EVENT, }; enum { UVERBS_ID_DRIVER_NS = 1UL << UVERBS_ID_NS_SHIFT, UVERBS_ATTR_UHW_IN = UVERBS_ID_DRIVER_NS, UVERBS_ATTR_UHW_OUT, UVERBS_ID_DRIVER_NS_WITH_UHW, }; enum uverbs_methods_device { UVERBS_METHOD_INVOKE_WRITE, UVERBS_METHOD_INFO_HANDLES, UVERBS_METHOD_QUERY_PORT, UVERBS_METHOD_GET_CONTEXT, UVERBS_METHOD_QUERY_CONTEXT, UVERBS_METHOD_QUERY_GID_TABLE, UVERBS_METHOD_QUERY_GID_ENTRY, }; enum uverbs_attrs_invoke_write_cmd_attr_ids { UVERBS_ATTR_CORE_IN, UVERBS_ATTR_CORE_OUT, UVERBS_ATTR_WRITE_CMD, }; enum uverbs_attrs_query_port_cmd_attr_ids { UVERBS_ATTR_QUERY_PORT_PORT_NUM, UVERBS_ATTR_QUERY_PORT_RESP, }; enum uverbs_attrs_get_context_attr_ids { UVERBS_ATTR_GET_CONTEXT_NUM_COMP_VECTORS, UVERBS_ATTR_GET_CONTEXT_CORE_SUPPORT, UVERBS_ATTR_GET_CONTEXT_FD_ARR, }; enum uverbs_attrs_query_context_attr_ids { UVERBS_ATTR_QUERY_CONTEXT_NUM_COMP_VECTORS, UVERBS_ATTR_QUERY_CONTEXT_CORE_SUPPORT, }; enum uverbs_attrs_create_cq_cmd_attr_ids { UVERBS_ATTR_CREATE_CQ_HANDLE, UVERBS_ATTR_CREATE_CQ_CQE, UVERBS_ATTR_CREATE_CQ_USER_HANDLE, UVERBS_ATTR_CREATE_CQ_COMP_CHANNEL, UVERBS_ATTR_CREATE_CQ_COMP_VECTOR, UVERBS_ATTR_CREATE_CQ_FLAGS, UVERBS_ATTR_CREATE_CQ_RESP_CQE, UVERBS_ATTR_CREATE_CQ_EVENT_FD, }; enum uverbs_attrs_destroy_cq_cmd_attr_ids { UVERBS_ATTR_DESTROY_CQ_HANDLE, UVERBS_ATTR_DESTROY_CQ_RESP, }; enum uverbs_attrs_create_flow_action_esp { UVERBS_ATTR_CREATE_FLOW_ACTION_ESP_HANDLE, UVERBS_ATTR_FLOW_ACTION_ESP_ATTRS, UVERBS_ATTR_FLOW_ACTION_ESP_ESN, UVERBS_ATTR_FLOW_ACTION_ESP_KEYMAT, UVERBS_ATTR_FLOW_ACTION_ESP_REPLAY, UVERBS_ATTR_FLOW_ACTION_ESP_ENCAP, }; enum uverbs_attrs_modify_flow_action_esp { UVERBS_ATTR_MODIFY_FLOW_ACTION_ESP_HANDLE = UVERBS_ATTR_CREATE_FLOW_ACTION_ESP_HANDLE, }; enum uverbs_attrs_destroy_flow_action_esp { UVERBS_ATTR_DESTROY_FLOW_ACTION_HANDLE, }; enum uverbs_attrs_create_qp_cmd_attr_ids { UVERBS_ATTR_CREATE_QP_HANDLE, UVERBS_ATTR_CREATE_QP_XRCD_HANDLE, UVERBS_ATTR_CREATE_QP_PD_HANDLE, UVERBS_ATTR_CREATE_QP_SRQ_HANDLE, UVERBS_ATTR_CREATE_QP_SEND_CQ_HANDLE, UVERBS_ATTR_CREATE_QP_RECV_CQ_HANDLE, UVERBS_ATTR_CREATE_QP_IND_TABLE_HANDLE, UVERBS_ATTR_CREATE_QP_USER_HANDLE, UVERBS_ATTR_CREATE_QP_CAP, UVERBS_ATTR_CREATE_QP_TYPE, UVERBS_ATTR_CREATE_QP_FLAGS, UVERBS_ATTR_CREATE_QP_SOURCE_QPN, UVERBS_ATTR_CREATE_QP_EVENT_FD, UVERBS_ATTR_CREATE_QP_RESP_CAP, UVERBS_ATTR_CREATE_QP_RESP_QP_NUM, }; enum uverbs_attrs_destroy_qp_cmd_attr_ids { UVERBS_ATTR_DESTROY_QP_HANDLE, UVERBS_ATTR_DESTROY_QP_RESP, }; enum uverbs_methods_qp { UVERBS_METHOD_QP_CREATE, UVERBS_METHOD_QP_DESTROY, }; enum uverbs_attrs_create_srq_cmd_attr_ids { UVERBS_ATTR_CREATE_SRQ_HANDLE, UVERBS_ATTR_CREATE_SRQ_PD_HANDLE, UVERBS_ATTR_CREATE_SRQ_XRCD_HANDLE, UVERBS_ATTR_CREATE_SRQ_CQ_HANDLE, UVERBS_ATTR_CREATE_SRQ_USER_HANDLE, UVERBS_ATTR_CREATE_SRQ_MAX_WR, UVERBS_ATTR_CREATE_SRQ_MAX_SGE, UVERBS_ATTR_CREATE_SRQ_LIMIT, UVERBS_ATTR_CREATE_SRQ_MAX_NUM_TAGS, UVERBS_ATTR_CREATE_SRQ_TYPE, UVERBS_ATTR_CREATE_SRQ_EVENT_FD, UVERBS_ATTR_CREATE_SRQ_RESP_MAX_WR, UVERBS_ATTR_CREATE_SRQ_RESP_MAX_SGE, UVERBS_ATTR_CREATE_SRQ_RESP_SRQ_NUM, }; enum uverbs_attrs_destroy_srq_cmd_attr_ids { UVERBS_ATTR_DESTROY_SRQ_HANDLE, UVERBS_ATTR_DESTROY_SRQ_RESP, }; enum uverbs_methods_srq { UVERBS_METHOD_SRQ_CREATE, UVERBS_METHOD_SRQ_DESTROY, }; enum uverbs_methods_cq { UVERBS_METHOD_CQ_CREATE, UVERBS_METHOD_CQ_DESTROY, }; enum uverbs_attrs_create_wq_cmd_attr_ids { UVERBS_ATTR_CREATE_WQ_HANDLE, UVERBS_ATTR_CREATE_WQ_PD_HANDLE, UVERBS_ATTR_CREATE_WQ_CQ_HANDLE, UVERBS_ATTR_CREATE_WQ_USER_HANDLE, UVERBS_ATTR_CREATE_WQ_TYPE, UVERBS_ATTR_CREATE_WQ_EVENT_FD, UVERBS_ATTR_CREATE_WQ_MAX_WR, UVERBS_ATTR_CREATE_WQ_MAX_SGE, UVERBS_ATTR_CREATE_WQ_FLAGS, UVERBS_ATTR_CREATE_WQ_RESP_MAX_WR, UVERBS_ATTR_CREATE_WQ_RESP_MAX_SGE, UVERBS_ATTR_CREATE_WQ_RESP_WQ_NUM, }; enum uverbs_attrs_destroy_wq_cmd_attr_ids { UVERBS_ATTR_DESTROY_WQ_HANDLE, UVERBS_ATTR_DESTROY_WQ_RESP, }; enum uverbs_methods_wq { UVERBS_METHOD_WQ_CREATE, UVERBS_METHOD_WQ_DESTROY, }; enum uverbs_methods_actions_flow_action_ops { UVERBS_METHOD_FLOW_ACTION_ESP_CREATE, UVERBS_METHOD_FLOW_ACTION_DESTROY, UVERBS_METHOD_FLOW_ACTION_ESP_MODIFY, }; enum uverbs_attrs_alloc_dm_cmd_attr_ids { UVERBS_ATTR_ALLOC_DM_HANDLE, UVERBS_ATTR_ALLOC_DM_LENGTH, UVERBS_ATTR_ALLOC_DM_ALIGNMENT, }; enum uverbs_attrs_free_dm_cmd_attr_ids { UVERBS_ATTR_FREE_DM_HANDLE, }; enum uverbs_methods_dm { UVERBS_METHOD_DM_ALLOC, UVERBS_METHOD_DM_FREE, }; enum uverbs_attrs_reg_dm_mr_cmd_attr_ids { UVERBS_ATTR_REG_DM_MR_HANDLE, UVERBS_ATTR_REG_DM_MR_OFFSET, UVERBS_ATTR_REG_DM_MR_LENGTH, UVERBS_ATTR_REG_DM_MR_PD_HANDLE, UVERBS_ATTR_REG_DM_MR_ACCESS_FLAGS, UVERBS_ATTR_REG_DM_MR_DM_HANDLE, UVERBS_ATTR_REG_DM_MR_RESP_LKEY, UVERBS_ATTR_REG_DM_MR_RESP_RKEY, }; enum uverbs_methods_mr { UVERBS_METHOD_DM_MR_REG, UVERBS_METHOD_MR_DESTROY, UVERBS_METHOD_ADVISE_MR, UVERBS_METHOD_QUERY_MR, UVERBS_METHOD_REG_DMABUF_MR, }; enum uverbs_attrs_mr_destroy_ids { UVERBS_ATTR_DESTROY_MR_HANDLE, }; enum uverbs_attrs_advise_mr_cmd_attr_ids { UVERBS_ATTR_ADVISE_MR_PD_HANDLE, UVERBS_ATTR_ADVISE_MR_ADVICE, UVERBS_ATTR_ADVISE_MR_FLAGS, UVERBS_ATTR_ADVISE_MR_SGE_LIST, }; enum uverbs_attrs_query_mr_cmd_attr_ids { UVERBS_ATTR_QUERY_MR_HANDLE, UVERBS_ATTR_QUERY_MR_RESP_LKEY, UVERBS_ATTR_QUERY_MR_RESP_RKEY, UVERBS_ATTR_QUERY_MR_RESP_LENGTH, UVERBS_ATTR_QUERY_MR_RESP_IOVA, }; enum uverbs_attrs_reg_dmabuf_mr_cmd_attr_ids { UVERBS_ATTR_REG_DMABUF_MR_HANDLE, UVERBS_ATTR_REG_DMABUF_MR_PD_HANDLE, UVERBS_ATTR_REG_DMABUF_MR_OFFSET, UVERBS_ATTR_REG_DMABUF_MR_LENGTH, UVERBS_ATTR_REG_DMABUF_MR_IOVA, UVERBS_ATTR_REG_DMABUF_MR_FD, UVERBS_ATTR_REG_DMABUF_MR_ACCESS_FLAGS, UVERBS_ATTR_REG_DMABUF_MR_RESP_LKEY, UVERBS_ATTR_REG_DMABUF_MR_RESP_RKEY, }; enum uverbs_attrs_create_counters_cmd_attr_ids { UVERBS_ATTR_CREATE_COUNTERS_HANDLE, }; enum uverbs_attrs_destroy_counters_cmd_attr_ids { UVERBS_ATTR_DESTROY_COUNTERS_HANDLE, }; enum uverbs_attrs_read_counters_cmd_attr_ids { UVERBS_ATTR_READ_COUNTERS_HANDLE, UVERBS_ATTR_READ_COUNTERS_BUFF, UVERBS_ATTR_READ_COUNTERS_FLAGS, }; enum uverbs_methods_actions_counters_ops { UVERBS_METHOD_COUNTERS_CREATE, UVERBS_METHOD_COUNTERS_DESTROY, UVERBS_METHOD_COUNTERS_READ, }; enum uverbs_attrs_info_handles_id { UVERBS_ATTR_INFO_OBJECT_ID, UVERBS_ATTR_INFO_TOTAL_HANDLES, UVERBS_ATTR_INFO_HANDLES_LIST, }; enum uverbs_methods_pd { UVERBS_METHOD_PD_DESTROY, }; enum uverbs_attrs_pd_destroy_ids { UVERBS_ATTR_DESTROY_PD_HANDLE, }; enum uverbs_methods_mw { UVERBS_METHOD_MW_DESTROY, }; enum uverbs_attrs_mw_destroy_ids { UVERBS_ATTR_DESTROY_MW_HANDLE, }; enum uverbs_methods_xrcd { UVERBS_METHOD_XRCD_DESTROY, }; enum uverbs_attrs_xrcd_destroy_ids { UVERBS_ATTR_DESTROY_XRCD_HANDLE, }; enum uverbs_methods_ah { UVERBS_METHOD_AH_DESTROY, }; enum uverbs_attrs_ah_destroy_ids { UVERBS_ATTR_DESTROY_AH_HANDLE, }; enum uverbs_methods_rwq_ind_tbl { UVERBS_METHOD_RWQ_IND_TBL_DESTROY, }; enum uverbs_attrs_rwq_ind_tbl_destroy_ids { UVERBS_ATTR_DESTROY_RWQ_IND_TBL_HANDLE, }; enum uverbs_methods_flow { UVERBS_METHOD_FLOW_DESTROY, }; enum uverbs_attrs_flow_destroy_ids { UVERBS_ATTR_DESTROY_FLOW_HANDLE, }; enum uverbs_method_async_event { UVERBS_METHOD_ASYNC_EVENT_ALLOC, }; enum uverbs_attrs_async_event_create { UVERBS_ATTR_ASYNC_EVENT_ALLOC_FD_HANDLE, }; enum uverbs_attrs_query_gid_table_cmd_attr_ids { UVERBS_ATTR_QUERY_GID_TABLE_ENTRY_SIZE, UVERBS_ATTR_QUERY_GID_TABLE_FLAGS, UVERBS_ATTR_QUERY_GID_TABLE_RESP_ENTRIES, UVERBS_ATTR_QUERY_GID_TABLE_RESP_NUM_ENTRIES, }; enum uverbs_attrs_query_gid_entry_cmd_attr_ids { UVERBS_ATTR_QUERY_GID_ENTRY_PORT, UVERBS_ATTR_QUERY_GID_ENTRY_GID_INDEX, UVERBS_ATTR_QUERY_GID_ENTRY_FLAGS, UVERBS_ATTR_QUERY_GID_ENTRY_RESP_ENTRY, }; #endif	9.67 KB	2026-03-24 10:01
📄 ib_user_ioctl_verbs.h /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) / / * Copyright (c) 2017-2018, Mellanox Technologies inc. All rights reserved. * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU * General Public License (GPL) Version 2, available from the file * COPYING in the main directory of this source tree, or the * OpenIB.org BSD license below: * * Redistribution and use in source and binary forms, with or * without modification, are permitted provided that the following * conditions are met: * * - Redistributions of source code must retain the above * copyright notice, this list of conditions and the following * disclaimer. * * - Redistributions in binary form must reproduce the above * copyright notice, this list of conditions and the following * disclaimer in the documentation and/or other materials * provided with the distribution. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. / #ifndef IB_USER_IOCTL_VERBS_H #define IB_USER_IOCTL_VERBS_H #include <linux/types.h> #include <rdma/ib_user_verbs.h> #ifndef RDMA_UAPI_PTR #define RDMA_UAPI_PTR(_type, _name) __aligned_u64 _name #endif #define IB_UVERBS_ACCESS_OPTIONAL_FIRST (1 << 20) #define IB_UVERBS_ACCESS_OPTIONAL_LAST (1 << 29) enum ib_uverbs_core_support { IB_UVERBS_CORE_SUPPORT_OPTIONAL_MR_ACCESS = 1 << 0, }; enum ib_uverbs_access_flags { IB_UVERBS_ACCESS_LOCAL_WRITE = 1 << 0, IB_UVERBS_ACCESS_REMOTE_WRITE = 1 << 1, IB_UVERBS_ACCESS_REMOTE_READ = 1 << 2, IB_UVERBS_ACCESS_REMOTE_ATOMIC = 1 << 3, IB_UVERBS_ACCESS_MW_BIND = 1 << 4, IB_UVERBS_ACCESS_ZERO_BASED = 1 << 5, IB_UVERBS_ACCESS_ON_DEMAND = 1 << 6, IB_UVERBS_ACCESS_HUGETLB = 1 << 7, IB_UVERBS_ACCESS_FLUSH_GLOBAL = 1 << 8, IB_UVERBS_ACCESS_FLUSH_PERSISTENT = 1 << 9, IB_UVERBS_ACCESS_RELAXED_ORDERING = IB_UVERBS_ACCESS_OPTIONAL_FIRST, IB_UVERBS_ACCESS_OPTIONAL_RANGE = ((IB_UVERBS_ACCESS_OPTIONAL_LAST << 1) - 1) & ~(IB_UVERBS_ACCESS_OPTIONAL_FIRST - 1) }; enum ib_uverbs_srq_type { IB_UVERBS_SRQT_BASIC, IB_UVERBS_SRQT_XRC, IB_UVERBS_SRQT_TM, }; enum ib_uverbs_wq_type { IB_UVERBS_WQT_RQ, }; enum ib_uverbs_wq_flags { IB_UVERBS_WQ_FLAGS_CVLAN_STRIPPING = 1 << 0, IB_UVERBS_WQ_FLAGS_SCATTER_FCS = 1 << 1, IB_UVERBS_WQ_FLAGS_DELAY_DROP = 1 << 2, IB_UVERBS_WQ_FLAGS_PCI_WRITE_END_PADDING = 1 << 3, }; enum ib_uverbs_qp_type { IB_UVERBS_QPT_RC = 2, IB_UVERBS_QPT_UC, IB_UVERBS_QPT_UD, IB_UVERBS_QPT_RAW_PACKET = 8, IB_UVERBS_QPT_XRC_INI, IB_UVERBS_QPT_XRC_TGT, IB_UVERBS_QPT_DRIVER = 0xFF, }; enum ib_uverbs_qp_create_flags { IB_UVERBS_QP_CREATE_BLOCK_MULTICAST_LOOPBACK = 1 << 1, IB_UVERBS_QP_CREATE_SCATTER_FCS = 1 << 8, IB_UVERBS_QP_CREATE_CVLAN_STRIPPING = 1 << 9, IB_UVERBS_QP_CREATE_PCI_WRITE_END_PADDING = 1 << 11, IB_UVERBS_QP_CREATE_SQ_SIG_ALL = 1 << 12, }; enum ib_uverbs_query_port_cap_flags { IB_UVERBS_PCF_SM = 1 << 1, IB_UVERBS_PCF_NOTICE_SUP = 1 << 2, IB_UVERBS_PCF_TRAP_SUP = 1 << 3, IB_UVERBS_PCF_OPT_IPD_SUP = 1 << 4, IB_UVERBS_PCF_AUTO_MIGR_SUP = 1 << 5, IB_UVERBS_PCF_SL_MAP_SUP = 1 << 6, IB_UVERBS_PCF_MKEY_NVRAM = 1 << 7, IB_UVERBS_PCF_PKEY_NVRAM = 1 << 8, IB_UVERBS_PCF_LED_INFO_SUP = 1 << 9, IB_UVERBS_PCF_SM_DISABLED = 1 << 10, IB_UVERBS_PCF_SYS_IMAGE_GUID_SUP = 1 << 11, IB_UVERBS_PCF_PKEY_SW_EXT_PORT_TRAP_SUP = 1 << 12, IB_UVERBS_PCF_EXTENDED_SPEEDS_SUP = 1 << 14, IB_UVERBS_PCF_CM_SUP = 1 << 16, IB_UVERBS_PCF_SNMP_TUNNEL_SUP = 1 << 17, IB_UVERBS_PCF_REINIT_SUP = 1 << 18, IB_UVERBS_PCF_DEVICE_MGMT_SUP = 1 << 19, IB_UVERBS_PCF_VENDOR_CLASS_SUP = 1 << 20, IB_UVERBS_PCF_DR_NOTICE_SUP = 1 << 21, IB_UVERBS_PCF_CAP_MASK_NOTICE_SUP = 1 << 22, IB_UVERBS_PCF_BOOT_MGMT_SUP = 1 << 23, IB_UVERBS_PCF_LINK_LATENCY_SUP = 1 << 24, IB_UVERBS_PCF_CLIENT_REG_SUP = 1 << 25, / * IsOtherLocalChangesNoticeSupported is aliased by IP_BASED_GIDS and * is inaccessible / IB_UVERBS_PCF_LINK_SPEED_WIDTH_TABLE_SUP = 1 << 27, IB_UVERBS_PCF_VENDOR_SPECIFIC_MADS_TABLE_SUP = 1 << 28, IB_UVERBS_PCF_MCAST_PKEY_TRAP_SUPPRESSION_SUP = 1 << 29, IB_UVERBS_PCF_MCAST_FDB_TOP_SUP = 1 << 30, IB_UVERBS_PCF_HIERARCHY_INFO_SUP = 1ULL << 31, / NOTE this is an internal flag, not an IBA flag / IB_UVERBS_PCF_IP_BASED_GIDS = 1 << 26, }; enum ib_uverbs_query_port_flags { IB_UVERBS_QPF_GRH_REQUIRED = 1 << 0, }; enum ib_uverbs_flow_action_esp_keymat { IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM, }; enum ib_uverbs_flow_action_esp_keymat_aes_gcm_iv_algo { IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ, }; struct ib_uverbs_flow_action_esp_keymat_aes_gcm { __aligned_u64 iv; __u32 iv_algo; / Use enum ib_uverbs_flow_action_esp_keymat_aes_gcm_iv_algo / __u32 salt; __u32 icv_len; __u32 key_len; __u32 aes_key[256 / 32]; }; enum ib_uverbs_flow_action_esp_replay { IB_UVERBS_FLOW_ACTION_ESP_REPLAY_NONE, IB_UVERBS_FLOW_ACTION_ESP_REPLAY_BMP, }; struct ib_uverbs_flow_action_esp_replay_bmp { __u32 size; }; enum ib_uverbs_flow_action_esp_flags { IB_UVERBS_FLOW_ACTION_ESP_FLAGS_INLINE_CRYPTO = 0UL << 0, / Default / IB_UVERBS_FLOW_ACTION_ESP_FLAGS_FULL_OFFLOAD = 1UL << 0, IB_UVERBS_FLOW_ACTION_ESP_FLAGS_TUNNEL = 0UL << 1, / Default / IB_UVERBS_FLOW_ACTION_ESP_FLAGS_TRANSPORT = 1UL << 1, IB_UVERBS_FLOW_ACTION_ESP_FLAGS_DECRYPT = 0UL << 2, / Default / IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT = 1UL << 2, IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW = 1UL << 3, }; struct ib_uverbs_flow_action_esp_encap { / This struct represents a list of pointers to flow_xxxx_filter that * encapsulates the payload in ESP tunnel mode. / RDMA_UAPI_PTR(void , val_ptr); /* pointer to a flow_xxxx_filter / RDMA_UAPI_PTR(struct ib_uverbs_flow_action_esp_encap , next_ptr); __u16 len; /* Len of the filter struct val_ptr points to / __u16 type; / Use flow_spec_type enum / }; struct ib_uverbs_flow_action_esp { __u32 spi; __u32 seq; __u32 tfc_pad; __u32 flags; __aligned_u64 hard_limit_pkts; }; enum ib_uverbs_read_counters_flags { / prefer read values from driver cache / IB_UVERBS_READ_COUNTERS_PREFER_CACHED = 1 << 0, }; enum ib_uverbs_advise_mr_advice { IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH, IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_WRITE, IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_NO_FAULT, }; enum ib_uverbs_advise_mr_flag { IB_UVERBS_ADVISE_MR_FLAG_FLUSH = 1 << 0, }; struct ib_uverbs_query_port_resp_ex { struct ib_uverbs_query_port_resp legacy_resp; __u16 port_cap_flags2; __u8 reserved[2]; __u32 active_speed_ex; }; struct ib_uverbs_qp_cap { __u32 max_send_wr; __u32 max_recv_wr; __u32 max_send_sge; __u32 max_recv_sge; __u32 max_inline_data; }; enum rdma_driver_id { RDMA_DRIVER_UNKNOWN, RDMA_DRIVER_MLX5, RDMA_DRIVER_MLX4, RDMA_DRIVER_CXGB3, RDMA_DRIVER_CXGB4, RDMA_DRIVER_MTHCA, RDMA_DRIVER_BNXT_RE, RDMA_DRIVER_OCRDMA, RDMA_DRIVER_NES, RDMA_DRIVER_I40IW, RDMA_DRIVER_IRDMA = RDMA_DRIVER_I40IW, RDMA_DRIVER_VMW_PVRDMA, RDMA_DRIVER_QEDR, RDMA_DRIVER_HNS, RDMA_DRIVER_USNIC, RDMA_DRIVER_RXE, RDMA_DRIVER_HFI1, RDMA_DRIVER_QIB, RDMA_DRIVER_EFA, RDMA_DRIVER_SIW, __RH_RESERVED_RDMA_DRIVER_ERDMA, RDMA_DRIVER_MANA, }; enum ib_uverbs_gid_type { IB_UVERBS_GID_TYPE_IB, IB_UVERBS_GID_TYPE_ROCE_V1, IB_UVERBS_GID_TYPE_ROCE_V2, }; struct ib_uverbs_gid_entry { __aligned_u64 gid[2]; __u32 gid_index; __u32 port_num; __u32 gid_type; __u32 netdev_ifindex; / It is 0 if there is no netdev associated with it */ }; #endif	7.77 KB	2026-03-24 10:01
📄 ib_user_mad.h /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) / / * Copyright (c) 2004 Topspin Communications. All rights reserved. * Copyright (c) 2005 Voltaire, Inc. All rights reserved. * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU * General Public License (GPL) Version 2, available from the file * COPYING in the main directory of this source tree, or the * OpenIB.org BSD license below: * * Redistribution and use in source and binary forms, with or * without modification, are permitted provided that the following * conditions are met: * * - Redistributions of source code must retain the above * copyright notice, this list of conditions and the following * disclaimer. * * - Redistributions in binary form must reproduce the above * copyright notice, this list of conditions and the following * disclaimer in the documentation and/or other materials * provided with the distribution. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. / #ifndef IB_USER_MAD_H #define IB_USER_MAD_H #include <linux/types.h> #include <rdma/rdma_user_ioctl.h> / * Increment this value if any changes that break userspace ABI * compatibility are made. / #define IB_USER_MAD_ABI_VERSION 5 / * Make sure that all structs defined in this file remain laid out so * that they pack the same way on 32-bit and 64-bit architectures (to * avoid incompatibility between 32-bit userspace and 64-bit kernels). / /* * ib_user_mad_hdr_old - Old version of MAD packet header without pkey_index * @id - ID of agent MAD received with/to be sent with * @status - 0 on successful receive, ETIMEDOUT if no response * received (transaction ID in data[] will be set to TID of original * request) (ignored on send) * @timeout_ms - Milliseconds to wait for response (unset on receive) * @retries - Number of automatic retries to attempt * @qpn - Remote QP number received from/to be sent to * @qkey - Remote Q_Key to be sent with (unset on receive) * @lid - Remote lid received from/to be sent to * @sl - Service level received with/to be sent with * @path_bits - Local path bits received with/to be sent with * @grh_present - If set, GRH was received/should be sent * @gid_index - Local GID index to send with (unset on receive) * @hop_limit - Hop limit in GRH * @traffic_class - Traffic class in GRH * @gid - Remote GID in GRH * @flow_label - Flow label in GRH / struct ib_user_mad_hdr_old { __u32 id; __u32 status; __u32 timeout_ms; __u32 retries; __u32 length; __be32 qpn; __be32 qkey; __be16 lid; __u8 sl; __u8 path_bits; __u8 grh_present; __u8 gid_index; __u8 hop_limit; __u8 traffic_class; __u8 gid[16]; __be32 flow_label; }; /* * ib_user_mad_hdr - MAD packet header * This layout allows specifying/receiving the P_Key index. To use * this capability, an application must call the * IB_USER_MAD_ENABLE_PKEY ioctl on the user MAD file handle before * any other actions with the file handle. * @id - ID of agent MAD received with/to be sent with * @status - 0 on successful receive, ETIMEDOUT if no response * received (transaction ID in data[] will be set to TID of original * request) (ignored on send) * @timeout_ms - Milliseconds to wait for response (unset on receive) * @retries - Number of automatic retries to attempt * @qpn - Remote QP number received from/to be sent to * @qkey - Remote Q_Key to be sent with (unset on receive) * @lid - Remote lid received from/to be sent to * @sl - Service level received with/to be sent with * @path_bits - Local path bits received with/to be sent with * @grh_present - If set, GRH was received/should be sent * @gid_index - Local GID index to send with (unset on receive) * @hop_limit - Hop limit in GRH * @traffic_class - Traffic class in GRH * @gid - Remote GID in GRH * @flow_label - Flow label in GRH * @pkey_index - P_Key index / struct ib_user_mad_hdr { __u32 id; __u32 status; __u32 timeout_ms; __u32 retries; __u32 length; __be32 qpn; __be32 qkey; __be16 lid; __u8 sl; __u8 path_bits; __u8 grh_present; __u8 gid_index; __u8 hop_limit; __u8 traffic_class; __u8 gid[16]; __be32 flow_label; __u16 pkey_index; __u8 reserved[6]; }; /* * ib_user_mad - MAD packet * @hdr - MAD packet header * @data - Contents of MAD * / struct ib_user_mad { struct ib_user_mad_hdr hdr; __aligned_u64 data[]; }; / * Earlier versions of this interface definition declared the * method_mask[] member as an array of __u32 but treated it as a * bitmap made up of longs in the kernel. This ambiguity meant that * 32-bit big-endian applications that can run on both 32-bit and * 64-bit kernels had no consistent ABI to rely on, and 64-bit * big-endian applications that treated method_mask as being made up * of 32-bit words would have their bitmap misinterpreted. * * To clear up this confusion, we change the declaration of * method_mask[] to use unsigned long and handle the conversion from * 32-bit userspace to 64-bit kernel for big-endian systems in the * compat_ioctl method. Unfortunately, to keep the structure layout * the same, we need the method_mask[] array to be aligned only to 4 * bytes even when long is 64 bits, which forces us into this ugly * typedef. / typedef unsigned long __attribute__((aligned(4))) packed_ulong; #define IB_USER_MAD_LONGS_PER_METHOD_MASK (128 / (8 sizeof (long))) /** * ib_user_mad_reg_req - MAD registration request * @id - Set by the kernel; used to identify agent in future requests. * @qpn - Queue pair number; must be 0 or 1. * @method_mask - The caller will receive unsolicited MADs for any method * where @method_mask = 1. * @mgmt_class - Indicates which management class of MADs should be receive * by the caller. This field is only required if the user wishes to * receive unsolicited MADs, otherwise it should be 0. * @mgmt_class_version - Indicates which version of MADs for the given * management class to receive. * @oui: Indicates IEEE OUI when mgmt_class is a vendor class * in the range from 0x30 to 0x4f. Otherwise not used. * @rmpp_version: If set, indicates the RMPP version used. * / struct ib_user_mad_reg_req { __u32 id; packed_ulong method_mask[IB_USER_MAD_LONGS_PER_METHOD_MASK]; __u8 qpn; __u8 mgmt_class; __u8 mgmt_class_version; __u8 oui[3]; __u8 rmpp_version; }; /* * ib_user_mad_reg_req2 - MAD registration request * * @id - Set by the _kernel_; used by userspace to identify the * registered agent in future requests. * @qpn - Queue pair number; must be 0 or 1. * @mgmt_class - Indicates which management class of MADs should be * receive by the caller. This field is only required if * the user wishes to receive unsolicited MADs, otherwise * it should be 0. * @mgmt_class_version - Indicates which version of MADs for the given * management class to receive. * @res - Ignored. * @flags - additional registration flags; Must be in the set of * flags defined in IB_USER_MAD_REG_FLAGS_CAP * @method_mask - The caller wishes to receive unsolicited MADs for the * methods whose bit(s) is(are) set. * @oui - Indicates IEEE OUI to use when mgmt_class is a vendor * class in the range from 0x30 to 0x4f. Otherwise not * used. * @rmpp_version - If set, indicates the RMPP version to use. / enum { IB_USER_MAD_USER_RMPP = (1 << 0), }; #define IB_USER_MAD_REG_FLAGS_CAP (IB_USER_MAD_USER_RMPP) struct ib_user_mad_reg_req2 { __u32 id; __u32 qpn; __u8 mgmt_class; __u8 mgmt_class_version; __u16 res; __u32 flags; __aligned_u64 method_mask[2]; __u32 oui; __u8 rmpp_version; __u8 reserved[3]; }; #endif / IB_USER_MAD_H */	8.33 KB	2026-03-24 10:01
📄 ib_user_sa.h /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) / / * Copyright (c) 2005 Intel Corporation. All rights reserved. * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU * General Public License (GPL) Version 2, available from the file * COPYING in the main directory of this source tree, or the * OpenIB.org BSD license below: * * Redistribution and use in source and binary forms, with or * without modification, are permitted provided that the following * conditions are met: * * - Redistributions of source code must retain the above * copyright notice, this list of conditions and the following * disclaimer. * * - Redistributions in binary form must reproduce the above * copyright notice, this list of conditions and the following * disclaimer in the documentation and/or other materials * provided with the distribution. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. / #ifndef IB_USER_SA_H #define IB_USER_SA_H #include <linux/types.h> enum { IB_PATH_GMP = 1, IB_PATH_PRIMARY = (1<<1), IB_PATH_ALTERNATE = (1<<2), IB_PATH_OUTBOUND = (1<<3), IB_PATH_INBOUND = (1<<4), IB_PATH_INBOUND_REVERSE = (1<<5), IB_PATH_BIDIRECTIONAL = IB_PATH_OUTBOUND \| IB_PATH_INBOUND_REVERSE }; struct ib_path_rec_data { __u32 flags; __u32 reserved; __u32 path_rec[16]; }; struct ib_user_path_rec { __u8 dgid[16]; __u8 sgid[16]; __be16 dlid; __be16 slid; __u32 raw_traffic; __be32 flow_label; __u32 reversible; __u32 mtu; __be16 pkey; __u8 hop_limit; __u8 traffic_class; __u8 numb_path; __u8 sl; __u8 mtu_selector; __u8 rate_selector; __u8 rate; __u8 packet_life_time_selector; __u8 packet_life_time; __u8 preference; }; #endif / IB_USER_SA_H */	2.25 KB	2026-03-24 10:01
📄 ib_user_verbs.h /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) / / * Copyright (c) 2005 Topspin Communications. All rights reserved. * Copyright (c) 2005, 2006 Cisco Systems. All rights reserved. * Copyright (c) 2005 PathScale, Inc. All rights reserved. * Copyright (c) 2006 Mellanox Technologies. All rights reserved. * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU * General Public License (GPL) Version 2, available from the file * COPYING in the main directory of this source tree, or the * OpenIB.org BSD license below: * * Redistribution and use in source and binary forms, with or * without modification, are permitted provided that the following * conditions are met: * * - Redistributions of source code must retain the above * copyright notice, this list of conditions and the following * disclaimer. * * - Redistributions in binary form must reproduce the above * copyright notice, this list of conditions and the following * disclaimer in the documentation and/or other materials * provided with the distribution. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. / #ifndef IB_USER_VERBS_H #define IB_USER_VERBS_H #include <linux/types.h> / * Increment this value if any changes that break userspace ABI * compatibility are made. / #define IB_USER_VERBS_ABI_VERSION 6 #define IB_USER_VERBS_CMD_THRESHOLD 50 enum ib_uverbs_write_cmds { IB_USER_VERBS_CMD_GET_CONTEXT, IB_USER_VERBS_CMD_QUERY_DEVICE, IB_USER_VERBS_CMD_QUERY_PORT, IB_USER_VERBS_CMD_ALLOC_PD, IB_USER_VERBS_CMD_DEALLOC_PD, IB_USER_VERBS_CMD_CREATE_AH, IB_USER_VERBS_CMD_MODIFY_AH, IB_USER_VERBS_CMD_QUERY_AH, IB_USER_VERBS_CMD_DESTROY_AH, IB_USER_VERBS_CMD_REG_MR, IB_USER_VERBS_CMD_REG_SMR, IB_USER_VERBS_CMD_REREG_MR, IB_USER_VERBS_CMD_QUERY_MR, IB_USER_VERBS_CMD_DEREG_MR, IB_USER_VERBS_CMD_ALLOC_MW, IB_USER_VERBS_CMD_BIND_MW, IB_USER_VERBS_CMD_DEALLOC_MW, IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL, IB_USER_VERBS_CMD_CREATE_CQ, IB_USER_VERBS_CMD_RESIZE_CQ, IB_USER_VERBS_CMD_DESTROY_CQ, IB_USER_VERBS_CMD_POLL_CQ, IB_USER_VERBS_CMD_PEEK_CQ, IB_USER_VERBS_CMD_REQ_NOTIFY_CQ, IB_USER_VERBS_CMD_CREATE_QP, IB_USER_VERBS_CMD_QUERY_QP, IB_USER_VERBS_CMD_MODIFY_QP, IB_USER_VERBS_CMD_DESTROY_QP, IB_USER_VERBS_CMD_POST_SEND, IB_USER_VERBS_CMD_POST_RECV, IB_USER_VERBS_CMD_ATTACH_MCAST, IB_USER_VERBS_CMD_DETACH_MCAST, IB_USER_VERBS_CMD_CREATE_SRQ, IB_USER_VERBS_CMD_MODIFY_SRQ, IB_USER_VERBS_CMD_QUERY_SRQ, IB_USER_VERBS_CMD_DESTROY_SRQ, IB_USER_VERBS_CMD_POST_SRQ_RECV, IB_USER_VERBS_CMD_OPEN_XRCD, IB_USER_VERBS_CMD_CLOSE_XRCD, IB_USER_VERBS_CMD_CREATE_XSRQ, IB_USER_VERBS_CMD_OPEN_QP, }; enum { IB_USER_VERBS_EX_CMD_QUERY_DEVICE = IB_USER_VERBS_CMD_QUERY_DEVICE, IB_USER_VERBS_EX_CMD_CREATE_CQ = IB_USER_VERBS_CMD_CREATE_CQ, IB_USER_VERBS_EX_CMD_CREATE_QP = IB_USER_VERBS_CMD_CREATE_QP, IB_USER_VERBS_EX_CMD_MODIFY_QP = IB_USER_VERBS_CMD_MODIFY_QP, IB_USER_VERBS_EX_CMD_CREATE_FLOW = IB_USER_VERBS_CMD_THRESHOLD, IB_USER_VERBS_EX_CMD_DESTROY_FLOW, IB_USER_VERBS_EX_CMD_CREATE_WQ, IB_USER_VERBS_EX_CMD_MODIFY_WQ, IB_USER_VERBS_EX_CMD_DESTROY_WQ, IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL, IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL, IB_USER_VERBS_EX_CMD_MODIFY_CQ }; / see IBA A19.4.1.1 Placement Types / enum ib_placement_type { IB_FLUSH_GLOBAL = 1U << 0, IB_FLUSH_PERSISTENT = 1U << 1, }; / see IBA A19.4.1.2 Selectivity Level / enum ib_selectivity_level { IB_FLUSH_RANGE = 0, IB_FLUSH_MR, }; / * Make sure that all structs defined in this file remain laid out so * that they pack the same way on 32-bit and 64-bit architectures (to * avoid incompatibility between 32-bit userspace and 64-bit kernels). * Specifically: * - Do not use pointer types -- pass pointers in __u64 instead. * - Make sure that any structure larger than 4 bytes is padded to a * multiple of 8 bytes. Otherwise the structure size will be * different between 32-bit and 64-bit architectures. / struct ib_uverbs_async_event_desc { __aligned_u64 element; __u32 event_type; / enum ib_event_type / __u32 reserved; }; struct ib_uverbs_comp_event_desc { __aligned_u64 cq_handle; }; struct ib_uverbs_cq_moderation_caps { __u16 max_cq_moderation_count; __u16 max_cq_moderation_period; __u32 reserved; }; / * All commands from userspace should start with a __u32 command field * followed by __u16 in_words and out_words fields (which give the * length of the command block and response buffer if any in 32-bit * words). The kernel driver will read these fields first and read * the rest of the command struct based on these value. / #define IB_USER_VERBS_CMD_COMMAND_MASK 0xff #define IB_USER_VERBS_CMD_FLAG_EXTENDED 0x80000000u struct ib_uverbs_cmd_hdr { __u32 command; __u16 in_words; __u16 out_words; }; struct ib_uverbs_ex_cmd_hdr { __aligned_u64 response; __u16 provider_in_words; __u16 provider_out_words; __u32 cmd_hdr_reserved; }; struct ib_uverbs_get_context { __aligned_u64 response; __aligned_u64 driver_data[]; }; struct ib_uverbs_get_context_resp { __u32 async_fd; __u32 num_comp_vectors; __aligned_u64 driver_data[]; }; struct ib_uverbs_query_device { __aligned_u64 response; __aligned_u64 driver_data[]; }; struct ib_uverbs_query_device_resp { __aligned_u64 fw_ver; __be64 node_guid; __be64 sys_image_guid; __aligned_u64 max_mr_size; __aligned_u64 page_size_cap; __u32 vendor_id; __u32 vendor_part_id; __u32 hw_ver; __u32 max_qp; __u32 max_qp_wr; __u32 device_cap_flags; __u32 max_sge; __u32 max_sge_rd; __u32 max_cq; __u32 max_cqe; __u32 max_mr; __u32 max_pd; __u32 max_qp_rd_atom; __u32 max_ee_rd_atom; __u32 max_res_rd_atom; __u32 max_qp_init_rd_atom; __u32 max_ee_init_rd_atom; __u32 atomic_cap; __u32 max_ee; __u32 max_rdd; __u32 max_mw; __u32 max_raw_ipv6_qp; __u32 max_raw_ethy_qp; __u32 max_mcast_grp; __u32 max_mcast_qp_attach; __u32 max_total_mcast_qp_attach; __u32 max_ah; __u32 max_fmr; __u32 max_map_per_fmr; __u32 max_srq; __u32 max_srq_wr; __u32 max_srq_sge; __u16 max_pkeys; __u8 local_ca_ack_delay; __u8 phys_port_cnt; __u8 reserved[4]; }; struct ib_uverbs_ex_query_device { __u32 comp_mask; __u32 reserved; }; struct ib_uverbs_odp_caps { __aligned_u64 general_caps; struct { __u32 rc_odp_caps; __u32 uc_odp_caps; __u32 ud_odp_caps; } per_transport_caps; __u32 reserved; }; struct ib_uverbs_rss_caps { / Corresponding bit will be set if qp type from * 'enum ib_qp_type' is supported, e.g. * supported_qpts \|= 1 << IB_QPT_UD / __u32 supported_qpts; __u32 max_rwq_indirection_tables; __u32 max_rwq_indirection_table_size; __u32 reserved; }; struct ib_uverbs_tm_caps { / Max size of rendezvous request message / __u32 max_rndv_hdr_size; / Max number of entries in tag matching list / __u32 max_num_tags; / TM flags / __u32 flags; / Max number of outstanding list operations / __u32 max_ops; / Max number of SGE in tag matching entry / __u32 max_sge; __u32 reserved; }; struct ib_uverbs_ex_query_device_resp { struct ib_uverbs_query_device_resp base; __u32 comp_mask; __u32 response_length; struct ib_uverbs_odp_caps odp_caps; __aligned_u64 timestamp_mask; __aligned_u64 hca_core_clock; / in KHZ / __aligned_u64 device_cap_flags_ex; struct ib_uverbs_rss_caps rss_caps; __u32 max_wq_type_rq; __u32 raw_packet_caps; struct ib_uverbs_tm_caps tm_caps; struct ib_uverbs_cq_moderation_caps cq_moderation_caps; __aligned_u64 max_dm_size; __u32 xrc_odp_caps; __u32 reserved; }; struct ib_uverbs_query_port { __aligned_u64 response; __u8 port_num; __u8 reserved[7]; __aligned_u64 driver_data[]; }; struct ib_uverbs_query_port_resp { __u32 port_cap_flags; / see ib_uverbs_query_port_cap_flags / __u32 max_msg_sz; __u32 bad_pkey_cntr; __u32 qkey_viol_cntr; __u32 gid_tbl_len; __u16 pkey_tbl_len; __u16 lid; __u16 sm_lid; __u8 state; __u8 max_mtu; __u8 active_mtu; __u8 lmc; __u8 max_vl_num; __u8 sm_sl; __u8 subnet_timeout; __u8 init_type_reply; __u8 active_width; __u8 active_speed; __u8 phys_state; __u8 link_layer; __u8 flags; / see ib_uverbs_query_port_flags / __u8 reserved; }; struct ib_uverbs_alloc_pd { __aligned_u64 response; __aligned_u64 driver_data[]; }; struct ib_uverbs_alloc_pd_resp { __u32 pd_handle; __u32 driver_data[]; }; struct ib_uverbs_dealloc_pd { __u32 pd_handle; }; struct ib_uverbs_open_xrcd { __aligned_u64 response; __u32 fd; __u32 oflags; __aligned_u64 driver_data[]; }; struct ib_uverbs_open_xrcd_resp { __u32 xrcd_handle; __u32 driver_data[]; }; struct ib_uverbs_close_xrcd { __u32 xrcd_handle; }; struct ib_uverbs_reg_mr { __aligned_u64 response; __aligned_u64 start; __aligned_u64 length; __aligned_u64 hca_va; __u32 pd_handle; __u32 access_flags; __aligned_u64 driver_data[]; }; struct ib_uverbs_reg_mr_resp { __u32 mr_handle; __u32 lkey; __u32 rkey; __u32 driver_data[]; }; struct ib_uverbs_rereg_mr { __aligned_u64 response; __u32 mr_handle; __u32 flags; __aligned_u64 start; __aligned_u64 length; __aligned_u64 hca_va; __u32 pd_handle; __u32 access_flags; __aligned_u64 driver_data[]; }; struct ib_uverbs_rereg_mr_resp { __u32 lkey; __u32 rkey; __aligned_u64 driver_data[]; }; struct ib_uverbs_dereg_mr { __u32 mr_handle; }; struct ib_uverbs_alloc_mw { __aligned_u64 response; __u32 pd_handle; __u8 mw_type; __u8 reserved[3]; __aligned_u64 driver_data[]; }; struct ib_uverbs_alloc_mw_resp { __u32 mw_handle; __u32 rkey; __aligned_u64 driver_data[]; }; struct ib_uverbs_dealloc_mw { __u32 mw_handle; }; struct ib_uverbs_create_comp_channel { __aligned_u64 response; }; struct ib_uverbs_create_comp_channel_resp { __u32 fd; }; struct ib_uverbs_create_cq { __aligned_u64 response; __aligned_u64 user_handle; __u32 cqe; __u32 comp_vector; __s32 comp_channel; __u32 reserved; __aligned_u64 driver_data[]; }; enum ib_uverbs_ex_create_cq_flags { IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION = 1 << 0, IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN = 1 << 1, }; struct ib_uverbs_ex_create_cq { __aligned_u64 user_handle; __u32 cqe; __u32 comp_vector; __s32 comp_channel; __u32 comp_mask; __u32 flags; / bitmask of ib_uverbs_ex_create_cq_flags / __u32 reserved; }; struct ib_uverbs_create_cq_resp { __u32 cq_handle; __u32 cqe; __aligned_u64 driver_data[0]; }; struct ib_uverbs_ex_create_cq_resp { struct ib_uverbs_create_cq_resp base; __u32 comp_mask; __u32 response_length; }; struct ib_uverbs_resize_cq { __aligned_u64 response; __u32 cq_handle; __u32 cqe; __aligned_u64 driver_data[]; }; struct ib_uverbs_resize_cq_resp { __u32 cqe; __u32 reserved; __aligned_u64 driver_data[]; }; struct ib_uverbs_poll_cq { __aligned_u64 response; __u32 cq_handle; __u32 ne; }; enum ib_uverbs_wc_opcode { IB_UVERBS_WC_SEND = 0, IB_UVERBS_WC_RDMA_WRITE = 1, IB_UVERBS_WC_RDMA_READ = 2, IB_UVERBS_WC_COMP_SWAP = 3, IB_UVERBS_WC_FETCH_ADD = 4, IB_UVERBS_WC_BIND_MW = 5, IB_UVERBS_WC_LOCAL_INV = 6, IB_UVERBS_WC_TSO = 7, IB_UVERBS_WC_FLUSH = 8, IB_UVERBS_WC_ATOMIC_WRITE = 9, }; struct ib_uverbs_wc { __aligned_u64 wr_id; __u32 status; __u32 opcode; __u32 vendor_err; __u32 byte_len; union { __be32 imm_data; __u32 invalidate_rkey; } ex; __u32 qp_num; __u32 src_qp; __u32 wc_flags; __u16 pkey_index; __u16 slid; __u8 sl; __u8 dlid_path_bits; __u8 port_num; __u8 reserved; }; struct ib_uverbs_poll_cq_resp { __u32 count; __u32 reserved; struct ib_uverbs_wc wc[]; }; struct ib_uverbs_req_notify_cq { __u32 cq_handle; __u32 solicited_only; }; struct ib_uverbs_destroy_cq { __aligned_u64 response; __u32 cq_handle; __u32 reserved; }; struct ib_uverbs_destroy_cq_resp { __u32 comp_events_reported; __u32 async_events_reported; }; struct ib_uverbs_global_route { __u8 dgid[16]; __u32 flow_label; __u8 sgid_index; __u8 hop_limit; __u8 traffic_class; __u8 reserved; }; struct ib_uverbs_ah_attr { struct ib_uverbs_global_route grh; __u16 dlid; __u8 sl; __u8 src_path_bits; __u8 static_rate; __u8 is_global; __u8 port_num; __u8 reserved; }; struct ib_uverbs_qp_attr { __u32 qp_attr_mask; __u32 qp_state; __u32 cur_qp_state; __u32 path_mtu; __u32 path_mig_state; __u32 qkey; __u32 rq_psn; __u32 sq_psn; __u32 dest_qp_num; __u32 qp_access_flags; struct ib_uverbs_ah_attr ah_attr; struct ib_uverbs_ah_attr alt_ah_attr; / ib_qp_cap / __u32 max_send_wr; __u32 max_recv_wr; __u32 max_send_sge; __u32 max_recv_sge; __u32 max_inline_data; __u16 pkey_index; __u16 alt_pkey_index; __u8 en_sqd_async_notify; __u8 sq_draining; __u8 max_rd_atomic; __u8 max_dest_rd_atomic; __u8 min_rnr_timer; __u8 port_num; __u8 timeout; __u8 retry_cnt; __u8 rnr_retry; __u8 alt_port_num; __u8 alt_timeout; __u8 reserved[5]; }; struct ib_uverbs_create_qp { __aligned_u64 response; __aligned_u64 user_handle; __u32 pd_handle; __u32 send_cq_handle; __u32 recv_cq_handle; __u32 srq_handle; __u32 max_send_wr; __u32 max_recv_wr; __u32 max_send_sge; __u32 max_recv_sge; __u32 max_inline_data; __u8 sq_sig_all; __u8 qp_type; __u8 is_srq; __u8 reserved; __aligned_u64 driver_data[]; }; enum ib_uverbs_create_qp_mask { IB_UVERBS_CREATE_QP_MASK_IND_TABLE = 1UL << 0, }; enum { IB_UVERBS_CREATE_QP_SUP_COMP_MASK = IB_UVERBS_CREATE_QP_MASK_IND_TABLE, }; struct ib_uverbs_ex_create_qp { __aligned_u64 user_handle; __u32 pd_handle; __u32 send_cq_handle; __u32 recv_cq_handle; __u32 srq_handle; __u32 max_send_wr; __u32 max_recv_wr; __u32 max_send_sge; __u32 max_recv_sge; __u32 max_inline_data; __u8 sq_sig_all; __u8 qp_type; __u8 is_srq; __u8 reserved; __u32 comp_mask; __u32 create_flags; __u32 rwq_ind_tbl_handle; __u32 source_qpn; }; struct ib_uverbs_open_qp { __aligned_u64 response; __aligned_u64 user_handle; __u32 pd_handle; __u32 qpn; __u8 qp_type; __u8 reserved[7]; __aligned_u64 driver_data[]; }; / also used for open response / struct ib_uverbs_create_qp_resp { __u32 qp_handle; __u32 qpn; __u32 max_send_wr; __u32 max_recv_wr; __u32 max_send_sge; __u32 max_recv_sge; __u32 max_inline_data; __u32 reserved; __u32 driver_data[0]; }; struct ib_uverbs_ex_create_qp_resp { struct ib_uverbs_create_qp_resp base; __u32 comp_mask; __u32 response_length; }; / * This struct needs to remain a multiple of 8 bytes to keep the * alignment of the modify QP parameters. / struct ib_uverbs_qp_dest { __u8 dgid[16]; __u32 flow_label; __u16 dlid; __u16 reserved; __u8 sgid_index; __u8 hop_limit; __u8 traffic_class; __u8 sl; __u8 src_path_bits; __u8 static_rate; __u8 is_global; __u8 port_num; }; struct ib_uverbs_query_qp { __aligned_u64 response; __u32 qp_handle; __u32 attr_mask; __aligned_u64 driver_data[]; }; struct ib_uverbs_query_qp_resp { struct ib_uverbs_qp_dest dest; struct ib_uverbs_qp_dest alt_dest; __u32 max_send_wr; __u32 max_recv_wr; __u32 max_send_sge; __u32 max_recv_sge; __u32 max_inline_data; __u32 qkey; __u32 rq_psn; __u32 sq_psn; __u32 dest_qp_num; __u32 qp_access_flags; __u16 pkey_index; __u16 alt_pkey_index; __u8 qp_state; __u8 cur_qp_state; __u8 path_mtu; __u8 path_mig_state; __u8 sq_draining; __u8 max_rd_atomic; __u8 max_dest_rd_atomic; __u8 min_rnr_timer; __u8 port_num; __u8 timeout; __u8 retry_cnt; __u8 rnr_retry; __u8 alt_port_num; __u8 alt_timeout; __u8 sq_sig_all; __u8 reserved[5]; __aligned_u64 driver_data[]; }; struct ib_uverbs_modify_qp { struct ib_uverbs_qp_dest dest; struct ib_uverbs_qp_dest alt_dest; __u32 qp_handle; __u32 attr_mask; __u32 qkey; __u32 rq_psn; __u32 sq_psn; __u32 dest_qp_num; __u32 qp_access_flags; __u16 pkey_index; __u16 alt_pkey_index; __u8 qp_state; __u8 cur_qp_state; __u8 path_mtu; __u8 path_mig_state; __u8 en_sqd_async_notify; __u8 max_rd_atomic; __u8 max_dest_rd_atomic; __u8 min_rnr_timer; __u8 port_num; __u8 timeout; __u8 retry_cnt; __u8 rnr_retry; __u8 alt_port_num; __u8 alt_timeout; __u8 reserved[2]; __aligned_u64 driver_data[0]; }; struct ib_uverbs_ex_modify_qp { struct ib_uverbs_modify_qp base; __u32 rate_limit; __u32 reserved; }; struct ib_uverbs_ex_modify_qp_resp { __u32 comp_mask; __u32 response_length; }; struct ib_uverbs_destroy_qp { __aligned_u64 response; __u32 qp_handle; __u32 reserved; }; struct ib_uverbs_destroy_qp_resp { __u32 events_reported; }; / * The ib_uverbs_sge structure isn't used anywhere, since we assume * the ib_sge structure is packed the same way on 32-bit and 64-bit * architectures in both kernel and user space. It's just here to * document the ABI. / struct ib_uverbs_sge { __aligned_u64 addr; __u32 length; __u32 lkey; }; enum ib_uverbs_wr_opcode { IB_UVERBS_WR_RDMA_WRITE = 0, IB_UVERBS_WR_RDMA_WRITE_WITH_IMM = 1, IB_UVERBS_WR_SEND = 2, IB_UVERBS_WR_SEND_WITH_IMM = 3, IB_UVERBS_WR_RDMA_READ = 4, IB_UVERBS_WR_ATOMIC_CMP_AND_SWP = 5, IB_UVERBS_WR_ATOMIC_FETCH_AND_ADD = 6, IB_UVERBS_WR_LOCAL_INV = 7, IB_UVERBS_WR_BIND_MW = 8, IB_UVERBS_WR_SEND_WITH_INV = 9, IB_UVERBS_WR_TSO = 10, IB_UVERBS_WR_RDMA_READ_WITH_INV = 11, IB_UVERBS_WR_MASKED_ATOMIC_CMP_AND_SWP = 12, IB_UVERBS_WR_MASKED_ATOMIC_FETCH_AND_ADD = 13, IB_UVERBS_WR_FLUSH = 14, IB_UVERBS_WR_ATOMIC_WRITE = 15, / Review enum ib_wr_opcode before modifying this / }; struct ib_uverbs_send_wr { __aligned_u64 wr_id; __u32 num_sge; __u32 opcode; / see enum ib_uverbs_wr_opcode / __u32 send_flags; union { __be32 imm_data; __u32 invalidate_rkey; } ex; union { struct { __aligned_u64 remote_addr; __u32 rkey; __u32 reserved; } rdma; struct { __aligned_u64 remote_addr; __aligned_u64 compare_add; __aligned_u64 swap; __u32 rkey; __u32 reserved; } atomic; struct { __u32 ah; __u32 remote_qpn; __u32 remote_qkey; __u32 reserved; } ud; } wr; }; struct ib_uverbs_post_send { __aligned_u64 response; __u32 qp_handle; __u32 wr_count; __u32 sge_count; __u32 wqe_size; struct ib_uverbs_send_wr send_wr[]; }; struct ib_uverbs_post_send_resp { __u32 bad_wr; }; struct ib_uverbs_recv_wr { __aligned_u64 wr_id; __u32 num_sge; __u32 reserved; }; struct ib_uverbs_post_recv { __aligned_u64 response; __u32 qp_handle; __u32 wr_count; __u32 sge_count; __u32 wqe_size; struct ib_uverbs_recv_wr recv_wr[]; }; struct ib_uverbs_post_recv_resp { __u32 bad_wr; }; struct ib_uverbs_post_srq_recv { __aligned_u64 response; __u32 srq_handle; __u32 wr_count; __u32 sge_count; __u32 wqe_size; struct ib_uverbs_recv_wr recv[]; }; struct ib_uverbs_post_srq_recv_resp { __u32 bad_wr; }; struct ib_uverbs_create_ah { __aligned_u64 response; __aligned_u64 user_handle; __u32 pd_handle; __u32 reserved; struct ib_uverbs_ah_attr attr; __aligned_u64 driver_data[]; }; struct ib_uverbs_create_ah_resp { __u32 ah_handle; __u32 driver_data[]; }; struct ib_uverbs_destroy_ah { __u32 ah_handle; }; struct ib_uverbs_attach_mcast { __u8 gid[16]; __u32 qp_handle; __u16 mlid; __u16 reserved; __aligned_u64 driver_data[]; }; struct ib_uverbs_detach_mcast { __u8 gid[16]; __u32 qp_handle; __u16 mlid; __u16 reserved; __aligned_u64 driver_data[]; }; struct ib_uverbs_flow_spec_hdr { __u32 type; __u16 size; __u16 reserved; / followed by flow_spec / __aligned_u64 flow_spec_data[0]; }; struct ib_uverbs_flow_eth_filter { __u8 dst_mac[6]; __u8 src_mac[6]; __be16 ether_type; __be16 vlan_tag; }; struct ib_uverbs_flow_spec_eth { union { struct ib_uverbs_flow_spec_hdr hdr; struct { __u32 type; __u16 size; __u16 reserved; }; }; struct ib_uverbs_flow_eth_filter val; struct ib_uverbs_flow_eth_filter mask; }; struct ib_uverbs_flow_ipv4_filter { __be32 src_ip; __be32 dst_ip; __u8 proto; __u8 tos; __u8 ttl; __u8 flags; }; struct ib_uverbs_flow_spec_ipv4 { union { struct ib_uverbs_flow_spec_hdr hdr; struct { __u32 type; __u16 size; __u16 reserved; }; }; struct ib_uverbs_flow_ipv4_filter val; struct ib_uverbs_flow_ipv4_filter mask; }; struct ib_uverbs_flow_tcp_udp_filter { __be16 dst_port; __be16 src_port; }; struct ib_uverbs_flow_spec_tcp_udp { union { struct ib_uverbs_flow_spec_hdr hdr; struct { __u32 type; __u16 size; __u16 reserved; }; }; struct ib_uverbs_flow_tcp_udp_filter val; struct ib_uverbs_flow_tcp_udp_filter mask; }; struct ib_uverbs_flow_ipv6_filter { __u8 src_ip[16]; __u8 dst_ip[16]; __be32 flow_label; __u8 next_hdr; __u8 traffic_class; __u8 hop_limit; __u8 reserved; }; struct ib_uverbs_flow_spec_ipv6 { union { struct ib_uverbs_flow_spec_hdr hdr; struct { __u32 type; __u16 size; __u16 reserved; }; }; struct ib_uverbs_flow_ipv6_filter val; struct ib_uverbs_flow_ipv6_filter mask; }; struct ib_uverbs_flow_spec_action_tag { union { struct ib_uverbs_flow_spec_hdr hdr; struct { __u32 type; __u16 size; __u16 reserved; }; }; __u32 tag_id; __u32 reserved1; }; struct ib_uverbs_flow_spec_action_drop { union { struct ib_uverbs_flow_spec_hdr hdr; struct { __u32 type; __u16 size; __u16 reserved; }; }; }; struct ib_uverbs_flow_spec_action_handle { union { struct ib_uverbs_flow_spec_hdr hdr; struct { __u32 type; __u16 size; __u16 reserved; }; }; __u32 handle; __u32 reserved1; }; struct ib_uverbs_flow_spec_action_count { union { struct ib_uverbs_flow_spec_hdr hdr; struct { __u32 type; __u16 size; __u16 reserved; }; }; __u32 handle; __u32 reserved1; }; struct ib_uverbs_flow_tunnel_filter { __be32 tunnel_id; }; struct ib_uverbs_flow_spec_tunnel { union { struct ib_uverbs_flow_spec_hdr hdr; struct { __u32 type; __u16 size; __u16 reserved; }; }; struct ib_uverbs_flow_tunnel_filter val; struct ib_uverbs_flow_tunnel_filter mask; }; struct ib_uverbs_flow_spec_esp_filter { __u32 spi; __u32 seq; }; struct ib_uverbs_flow_spec_esp { union { struct ib_uverbs_flow_spec_hdr hdr; struct { __u32 type; __u16 size; __u16 reserved; }; }; struct ib_uverbs_flow_spec_esp_filter val; struct ib_uverbs_flow_spec_esp_filter mask; }; struct ib_uverbs_flow_gre_filter { / c_ks_res0_ver field is bits 0-15 in offset 0 of a standard GRE header: * bit 0 - C - checksum bit. * bit 1 - reserved. set to 0. * bit 2 - key bit. * bit 3 - sequence number bit. * bits 4:12 - reserved. set to 0. * bits 13:15 - GRE version. / __be16 c_ks_res0_ver; __be16 protocol; __be32 key; }; struct ib_uverbs_flow_spec_gre { union { struct ib_uverbs_flow_spec_hdr hdr; struct { __u32 type; __u16 size; __u16 reserved; }; }; struct ib_uverbs_flow_gre_filter val; struct ib_uverbs_flow_gre_filter mask; }; struct ib_uverbs_flow_mpls_filter { / The field includes the entire MPLS label: * bits 0:19 - label field. * bits 20:22 - traffic class field. * bits 23 - bottom of stack bit. * bits 24:31 - ttl field. / __be32 label; }; struct ib_uverbs_flow_spec_mpls { union { struct ib_uverbs_flow_spec_hdr hdr; struct { __u32 type; __u16 size; __u16 reserved; }; }; struct ib_uverbs_flow_mpls_filter val; struct ib_uverbs_flow_mpls_filter mask; }; struct ib_uverbs_flow_attr { __u32 type; __u16 size; __u16 priority; __u8 num_of_specs; __u8 reserved[2]; __u8 port; __u32 flags; / Following are the optional layers according to user request * struct ib_flow_spec_xxx * struct ib_flow_spec_yyy / struct ib_uverbs_flow_spec_hdr flow_specs[]; }; struct ib_uverbs_create_flow { __u32 comp_mask; __u32 qp_handle; struct ib_uverbs_flow_attr flow_attr; }; struct ib_uverbs_create_flow_resp { __u32 comp_mask; __u32 flow_handle; }; struct ib_uverbs_destroy_flow { __u32 comp_mask; __u32 flow_handle; }; struct ib_uverbs_create_srq { __aligned_u64 response; __aligned_u64 user_handle; __u32 pd_handle; __u32 max_wr; __u32 max_sge; __u32 srq_limit; __aligned_u64 driver_data[]; }; struct ib_uverbs_create_xsrq { __aligned_u64 response; __aligned_u64 user_handle; __u32 srq_type; __u32 pd_handle; __u32 max_wr; __u32 max_sge; __u32 srq_limit; __u32 max_num_tags; __u32 xrcd_handle; __u32 cq_handle; __aligned_u64 driver_data[]; }; struct ib_uverbs_create_srq_resp { __u32 srq_handle; __u32 max_wr; __u32 max_sge; __u32 srqn; __u32 driver_data[]; }; struct ib_uverbs_modify_srq { __u32 srq_handle; __u32 attr_mask; __u32 max_wr; __u32 srq_limit; __aligned_u64 driver_data[]; }; struct ib_uverbs_query_srq { __aligned_u64 response; __u32 srq_handle; __u32 reserved; __aligned_u64 driver_data[]; }; struct ib_uverbs_query_srq_resp { __u32 max_wr; __u32 max_sge; __u32 srq_limit; __u32 reserved; }; struct ib_uverbs_destroy_srq { __aligned_u64 response; __u32 srq_handle; __u32 reserved; }; struct ib_uverbs_destroy_srq_resp { __u32 events_reported; }; struct ib_uverbs_ex_create_wq { __u32 comp_mask; __u32 wq_type; __aligned_u64 user_handle; __u32 pd_handle; __u32 cq_handle; __u32 max_wr; __u32 max_sge; __u32 create_flags; / Use enum ib_wq_flags / __u32 reserved; }; struct ib_uverbs_ex_create_wq_resp { __u32 comp_mask; __u32 response_length; __u32 wq_handle; __u32 max_wr; __u32 max_sge; __u32 wqn; }; struct ib_uverbs_ex_destroy_wq { __u32 comp_mask; __u32 wq_handle; }; struct ib_uverbs_ex_destroy_wq_resp { __u32 comp_mask; __u32 response_length; __u32 events_reported; __u32 reserved; }; struct ib_uverbs_ex_modify_wq { __u32 attr_mask; __u32 wq_handle; __u32 wq_state; __u32 curr_wq_state; __u32 flags; / Use enum ib_wq_flags / __u32 flags_mask; / Use enum ib_wq_flags / }; / Prevent memory allocation rather than max expected size / #define IB_USER_VERBS_MAX_LOG_IND_TBL_SIZE 0x0d struct ib_uverbs_ex_create_rwq_ind_table { __u32 comp_mask; __u32 log_ind_tbl_size; / Following are the wq handles according to log_ind_tbl_size * wq_handle1 * wq_handle2 / __u32 wq_handles[]; }; struct ib_uverbs_ex_create_rwq_ind_table_resp { __u32 comp_mask; __u32 response_length; __u32 ind_tbl_handle; __u32 ind_tbl_num; }; struct ib_uverbs_ex_destroy_rwq_ind_table { __u32 comp_mask; __u32 ind_tbl_handle; }; struct ib_uverbs_cq_moderation { __u16 cq_count; __u16 cq_period; }; struct ib_uverbs_ex_modify_cq { __u32 cq_handle; __u32 attr_mask; struct ib_uverbs_cq_moderation attr; __u32 reserved; }; #define IB_DEVICE_NAME_MAX 64 / * bits 9, 15, 16, 19, 22, 27, 30, 31, 32, 33, 35 and 37 may be set by old * kernels and should not be used. / enum ib_uverbs_device_cap_flags { IB_UVERBS_DEVICE_RESIZE_MAX_WR = 1 << 0, IB_UVERBS_DEVICE_BAD_PKEY_CNTR = 1 << 1, IB_UVERBS_DEVICE_BAD_QKEY_CNTR = 1 << 2, IB_UVERBS_DEVICE_RAW_MULTI = 1 << 3, IB_UVERBS_DEVICE_AUTO_PATH_MIG = 1 << 4, IB_UVERBS_DEVICE_CHANGE_PHY_PORT = 1 << 5, IB_UVERBS_DEVICE_UD_AV_PORT_ENFORCE = 1 << 6, IB_UVERBS_DEVICE_CURR_QP_STATE_MOD = 1 << 7, IB_UVERBS_DEVICE_SHUTDOWN_PORT = 1 << 8, / IB_UVERBS_DEVICE_INIT_TYPE = 1 << 9, (not in use) / IB_UVERBS_DEVICE_PORT_ACTIVE_EVENT = 1 << 10, IB_UVERBS_DEVICE_SYS_IMAGE_GUID = 1 << 11, IB_UVERBS_DEVICE_RC_RNR_NAK_GEN = 1 << 12, IB_UVERBS_DEVICE_SRQ_RESIZE = 1 << 13, IB_UVERBS_DEVICE_N_NOTIFY_CQ = 1 << 14, IB_UVERBS_DEVICE_MEM_WINDOW = 1 << 17, IB_UVERBS_DEVICE_UD_IP_CSUM = 1 << 18, IB_UVERBS_DEVICE_XRC = 1 << 20, IB_UVERBS_DEVICE_MEM_MGT_EXTENSIONS = 1 << 21, IB_UVERBS_DEVICE_MEM_WINDOW_TYPE_2A = 1 << 23, IB_UVERBS_DEVICE_MEM_WINDOW_TYPE_2B = 1 << 24, IB_UVERBS_DEVICE_RC_IP_CSUM = 1 << 25, / Deprecated. Please use IB_UVERBS_RAW_PACKET_CAP_IP_CSUM. / IB_UVERBS_DEVICE_RAW_IP_CSUM = 1 << 26, IB_UVERBS_DEVICE_MANAGED_FLOW_STEERING = 1 << 29, / Deprecated. Please use IB_UVERBS_RAW_PACKET_CAP_SCATTER_FCS. / IB_UVERBS_DEVICE_RAW_SCATTER_FCS = 1ULL << 34, IB_UVERBS_DEVICE_PCI_WRITE_END_PADDING = 1ULL << 36, / Flush placement types / IB_UVERBS_DEVICE_FLUSH_GLOBAL = 1ULL << 38, IB_UVERBS_DEVICE_FLUSH_PERSISTENT = 1ULL << 39, / Atomic write attributes / IB_UVERBS_DEVICE_ATOMIC_WRITE = 1ULL << 40, }; enum ib_uverbs_raw_packet_caps { IB_UVERBS_RAW_PACKET_CAP_CVLAN_STRIPPING = 1 << 0, IB_UVERBS_RAW_PACKET_CAP_SCATTER_FCS = 1 << 1, IB_UVERBS_RAW_PACKET_CAP_IP_CSUM = 1 << 2, IB_UVERBS_RAW_PACKET_CAP_DELAY_DROP = 1 << 3, }; #endif / IB_USER_VERBS_H */	28.29 KB	2026-03-24 10:01
📄 irdma-abi.h /* SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB / / * Copyright (c) 2006 - 2021 Intel Corporation. All rights reserved. * Copyright (c) 2005 Topspin Communications. All rights reserved. * Copyright (c) 2005 Cisco Systems. All rights reserved. * Copyright (c) 2005 Open Grid Computing, Inc. All rights reserved. / #ifndef IRDMA_ABI_H #define IRDMA_ABI_H #include <linux/types.h> / irdma must support legacy GEN_1 i40iw kernel * and user-space whose last ABI ver is 5 / #define IRDMA_ABI_VER 5 enum irdma_memreg_type { IRDMA_MEMREG_TYPE_MEM = 0, IRDMA_MEMREG_TYPE_QP = 1, IRDMA_MEMREG_TYPE_CQ = 2, }; enum { IRDMA_ALLOC_UCTX_USE_RAW_ATTR = 1 << 0, IRDMA_ALLOC_UCTX_MIN_HW_WQ_SIZE = 1 << 1, }; struct irdma_alloc_ucontext_req { __u32 rsvd32; __u8 userspace_ver; __u8 rsvd8[3]; __aligned_u64 comp_mask; }; struct irdma_alloc_ucontext_resp { __u32 max_pds; __u32 max_qps; __u32 wq_size; / size of the WQs (SQ+RQ) in the mmaped area / __u8 kernel_ver; __u8 rsvd[3]; __aligned_u64 feature_flags; __aligned_u64 db_mmap_key; __u32 max_hw_wq_frags; __u32 max_hw_read_sges; __u32 max_hw_inline; __u32 max_hw_rq_quanta; __u32 max_hw_wq_quanta; __u32 min_hw_cq_size; __u32 max_hw_cq_size; __u16 max_hw_sq_chunk; __u8 hw_rev; __u8 rsvd2; __aligned_u64 comp_mask; __u16 min_hw_wq_size; __u8 rsvd3[6]; }; struct irdma_alloc_pd_resp { __u32 pd_id; __u8 rsvd[4]; }; struct irdma_resize_cq_req { __aligned_u64 user_cq_buffer; }; struct irdma_create_cq_req { __aligned_u64 user_cq_buf; __aligned_u64 user_shadow_area; }; struct irdma_create_qp_req { __aligned_u64 user_wqe_bufs; __aligned_u64 user_compl_ctx; }; struct irdma_mem_reg_req { __u16 reg_type; / enum irdma_memreg_type / __u16 cq_pages; __u16 rq_pages; __u16 sq_pages; }; struct irdma_modify_qp_req { __u8 sq_flush; __u8 rq_flush; __u8 rsvd[6]; }; struct irdma_create_cq_resp { __u32 cq_id; __u32 cq_size; }; struct irdma_create_qp_resp { __u32 qp_id; __u32 actual_sq_size; __u32 actual_rq_size; __u32 irdma_drv_opt; __u16 push_idx; __u8 lsmm; __u8 rsvd; __u32 qp_caps; }; struct irdma_modify_qp_resp { __aligned_u64 push_wqe_mmap_key; __aligned_u64 push_db_mmap_key; __u16 push_offset; __u8 push_valid; __u8 rsvd[5]; }; struct irdma_create_ah_resp { __u32 ah_id; __u8 rsvd[4]; }; #endif / IRDMA_ABI_H */	2.32 KB	2026-03-24 10:01
📄 mana-abi.h /* SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) / / * Copyright (c) 2022, Microsoft Corporation. All rights reserved. / #ifndef MANA_ABI_USER_H #define MANA_ABI_USER_H #include <linux/types.h> #include <rdma/ib_user_ioctl_verbs.h> / * Increment this value if any changes that break userspace ABI * compatibility are made. / #define MANA_IB_UVERBS_ABI_VERSION 1 enum mana_ib_create_cq_flags { MANA_IB_CREATE_RNIC_CQ = 1 << 0, }; struct mana_ib_create_cq { __aligned_u64 buf_addr; __u16 flags; __u16 reserved0; __u32 reserved1; }; struct mana_ib_create_cq_resp { __u32 cqid; __u32 reserved; }; struct mana_ib_create_qp { __aligned_u64 sq_buf_addr; __u32 sq_buf_size; __u32 port; }; struct mana_ib_create_qp_resp { __u32 sqid; __u32 cqid; __u32 tx_vp_offset; __u32 reserved; }; struct mana_ib_create_rc_qp { __aligned_u64 queue_buf[4]; __u32 queue_size[4]; }; struct mana_ib_create_rc_qp_resp { __u32 queue_id[4]; }; struct mana_ib_create_wq { __aligned_u64 wq_buf_addr; __u32 wq_buf_size; __u32 reserved; }; / RX Hash function flags */ enum mana_ib_rx_hash_function_flags { MANA_IB_RX_HASH_FUNC_TOEPLITZ = 1 << 0, }; struct mana_ib_create_qp_rss { __aligned_u64 rx_hash_fields_mask; __u8 rx_hash_function; __u8 reserved[7]; __u32 rx_hash_key_len; __u8 rx_hash_key[40]; __u32 port; }; struct rss_resp_entry { __u32 cqid; __u32 wqid; }; struct mana_ib_create_qp_rss_resp { __aligned_u64 num_entries; struct rss_resp_entry entries[64]; }; #endif	1.48 KB	2026-03-24 10:01
📄 mlx4-abi.h /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) / / * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved. * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU * General Public License (GPL) Version 2, available from the file * COPYING in the main directory of this source tree, or the * OpenIB.org BSD license below: * * Redistribution and use in source and binary forms, with or * without modification, are permitted provided that the following * conditions are met: * * - Redistributions of source code must retain the above * copyright notice, this list of conditions and the following * disclaimer. * * - Redistributions in binary form must reproduce the above * copyright notice, this list of conditions and the following * disclaimer in the documentation and/or other materials * provided with the distribution. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. / #ifndef MLX4_ABI_USER_H #define MLX4_ABI_USER_H #include <linux/types.h> / * Increment this value if any changes that break userspace ABI * compatibility are made. / #define MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION 3 #define MLX4_IB_UVERBS_ABI_VERSION 4 / * Make sure that all structs defined in this file remain laid out so * that they pack the same way on 32-bit and 64-bit architectures (to * avoid incompatibility between 32-bit userspace and 64-bit kernels). * In particular do not use pointer types -- pass pointers in __u64 * instead. / struct mlx4_ib_alloc_ucontext_resp_v3 { __u32 qp_tab_size; __u16 bf_reg_size; __u16 bf_regs_per_page; }; enum { MLX4_USER_DEV_CAP_LARGE_CQE = 1L << 0, }; struct mlx4_ib_alloc_ucontext_resp { __u32 dev_caps; __u32 qp_tab_size; __u16 bf_reg_size; __u16 bf_regs_per_page; __u32 cqe_size; }; struct mlx4_ib_alloc_pd_resp { __u32 pdn; __u32 reserved; }; struct mlx4_ib_create_cq { __aligned_u64 buf_addr; __aligned_u64 db_addr; }; struct mlx4_ib_create_cq_resp { __u32 cqn; __u32 reserved; }; struct mlx4_ib_resize_cq { __aligned_u64 buf_addr; }; struct mlx4_ib_create_srq { __aligned_u64 buf_addr; __aligned_u64 db_addr; }; struct mlx4_ib_create_srq_resp { __u32 srqn; __u32 reserved; }; struct mlx4_ib_create_qp_rss { __aligned_u64 rx_hash_fields_mask; / Use enum mlx4_ib_rx_hash_fields / __u8 rx_hash_function; / Use enum mlx4_ib_rx_hash_function_flags / __u8 reserved[7]; __u8 rx_hash_key[40]; __u32 comp_mask; __u32 reserved1; }; struct mlx4_ib_create_qp { __aligned_u64 buf_addr; __aligned_u64 db_addr; __u8 log_sq_bb_count; __u8 log_sq_stride; __u8 sq_no_prefetch; __u8 reserved; __u32 inl_recv_sz; }; struct mlx4_ib_create_wq { __aligned_u64 buf_addr; __aligned_u64 db_addr; __u8 log_range_size; __u8 reserved[3]; __u32 comp_mask; }; struct mlx4_ib_modify_wq { __u32 comp_mask; __u32 reserved; }; struct mlx4_ib_create_rwq_ind_tbl_resp { __u32 response_length; __u32 reserved; }; / RX Hash function flags / enum mlx4_ib_rx_hash_function_flags { MLX4_IB_RX_HASH_FUNC_TOEPLITZ = 1 << 0, }; / * RX Hash flags, these flags allows to set which incoming packet's field should * participates in RX Hash. Each flag represent certain packet's field, * when the flag is set the field that is represented by the flag will * participate in RX Hash calculation. / enum mlx4_ib_rx_hash_fields { MLX4_IB_RX_HASH_SRC_IPV4 = 1 << 0, MLX4_IB_RX_HASH_DST_IPV4 = 1 << 1, MLX4_IB_RX_HASH_SRC_IPV6 = 1 << 2, MLX4_IB_RX_HASH_DST_IPV6 = 1 << 3, MLX4_IB_RX_HASH_SRC_PORT_TCP = 1 << 4, MLX4_IB_RX_HASH_DST_PORT_TCP = 1 << 5, MLX4_IB_RX_HASH_SRC_PORT_UDP = 1 << 6, MLX4_IB_RX_HASH_DST_PORT_UDP = 1 << 7, MLX4_IB_RX_HASH_INNER = 1ULL << 31, }; struct mlx4_ib_rss_caps { __aligned_u64 rx_hash_fields_mask; / enum mlx4_ib_rx_hash_fields / __u8 rx_hash_function; / enum mlx4_ib_rx_hash_function_flags / __u8 reserved[7]; }; enum query_device_resp_mask { MLX4_IB_QUERY_DEV_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0, }; struct mlx4_ib_tso_caps { __u32 max_tso; / Maximum tso payload size in bytes / / Corresponding bit will be set if qp type from * 'enum ib_qp_type' is supported. / __u32 supported_qpts; }; struct mlx4_uverbs_ex_query_device_resp { __u32 comp_mask; __u32 response_length; __aligned_u64 hca_core_clock_offset; __u32 max_inl_recv_sz; __u32 reserved; struct mlx4_ib_rss_caps rss_caps; struct mlx4_ib_tso_caps tso_caps; }; #endif / MLX4_ABI_USER_H */	5 KB	2026-03-24 10:01
📄 mlx5-abi.h /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) / / * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU * General Public License (GPL) Version 2, available from the file * COPYING in the main directory of this source tree, or the * OpenIB.org BSD license below: * * Redistribution and use in source and binary forms, with or * without modification, are permitted provided that the following * conditions are met: * * - Redistributions of source code must retain the above * copyright notice, this list of conditions and the following * disclaimer. * * - Redistributions in binary form must reproduce the above * copyright notice, this list of conditions and the following * disclaimer in the documentation and/or other materials * provided with the distribution. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. / #ifndef MLX5_ABI_USER_H #define MLX5_ABI_USER_H #include <linux/types.h> #include <linux/if_ether.h> / For ETH_ALEN. / #include <rdma/ib_user_ioctl_verbs.h> #include <rdma/mlx5_user_ioctl_verbs.h> enum { MLX5_QP_FLAG_SIGNATURE = 1 << 0, MLX5_QP_FLAG_SCATTER_CQE = 1 << 1, MLX5_QP_FLAG_TUNNEL_OFFLOADS = 1 << 2, MLX5_QP_FLAG_BFREG_INDEX = 1 << 3, MLX5_QP_FLAG_TYPE_DCT = 1 << 4, MLX5_QP_FLAG_TYPE_DCI = 1 << 5, MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC = 1 << 6, MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC = 1 << 7, MLX5_QP_FLAG_ALLOW_SCATTER_CQE = 1 << 8, MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE = 1 << 9, MLX5_QP_FLAG_UAR_PAGE_INDEX = 1 << 10, MLX5_QP_FLAG_DCI_STREAM = 1 << 11, }; enum { MLX5_SRQ_FLAG_SIGNATURE = 1 << 0, }; enum { MLX5_WQ_FLAG_SIGNATURE = 1 << 0, }; / Increment this value if any changes that break userspace ABI * compatibility are made. / #define MLX5_IB_UVERBS_ABI_VERSION 1 / Make sure that all structs defined in this file remain laid out so * that they pack the same way on 32-bit and 64-bit architectures (to * avoid incompatibility between 32-bit userspace and 64-bit kernels). * In particular do not use pointer types -- pass pointers in __u64 * instead. / struct mlx5_ib_alloc_ucontext_req { __u32 total_num_bfregs; __u32 num_low_latency_bfregs; }; enum mlx5_lib_caps { MLX5_LIB_CAP_4K_UAR = (__u64)1 << 0, MLX5_LIB_CAP_DYN_UAR = (__u64)1 << 1, }; enum mlx5_ib_alloc_uctx_v2_flags { MLX5_IB_ALLOC_UCTX_DEVX = 1 << 0, }; struct mlx5_ib_alloc_ucontext_req_v2 { __u32 total_num_bfregs; __u32 num_low_latency_bfregs; __u32 flags; __u32 comp_mask; __u8 max_cqe_version; __u8 reserved0; __u16 reserved1; __u32 reserved2; __aligned_u64 lib_caps; }; enum mlx5_ib_alloc_ucontext_resp_mask { MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0, MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY = 1UL << 1, MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE = 1UL << 2, MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS = 1UL << 3, MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_REAL_TIME_TS = 1UL << 4, MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_MKEY_UPDATE_TAG = 1UL << 5, }; enum mlx5_user_cmds_supp_uhw { MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0, MLX5_USER_CMDS_SUPP_UHW_CREATE_AH = 1 << 1, }; / The eth_min_inline response value is set to off-by-one vs the FW * returned value to allow user-space to deal with older kernels. / enum mlx5_user_inline_mode { MLX5_USER_INLINE_MODE_NA, MLX5_USER_INLINE_MODE_NONE, MLX5_USER_INLINE_MODE_L2, MLX5_USER_INLINE_MODE_IP, MLX5_USER_INLINE_MODE_TCP_UDP, }; enum { MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM = 1 << 0, MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA = 1 << 1, MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING = 1 << 2, MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD = 1 << 3, MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN = 1 << 4, }; struct mlx5_ib_alloc_ucontext_resp { __u32 qp_tab_size; __u32 bf_reg_size; __u32 tot_bfregs; __u32 cache_line_size; __u16 max_sq_desc_sz; __u16 max_rq_desc_sz; __u32 max_send_wqebb; __u32 max_recv_wr; __u32 max_srq_recv_wr; __u16 num_ports; __u16 flow_action_flags; __u32 comp_mask; __u32 response_length; __u8 cqe_version; __u8 cmds_supp_uhw; __u8 eth_min_inline; __u8 clock_info_versions; __aligned_u64 hca_core_clock_offset; __u32 log_uar_size; __u32 num_uars_per_page; __u32 num_dyn_bfregs; __u32 dump_fill_mkey; }; struct mlx5_ib_alloc_pd_resp { __u32 pdn; }; struct mlx5_ib_tso_caps { __u32 max_tso; / Maximum tso payload size in bytes / / Corresponding bit will be set if qp type from * 'enum ib_qp_type' is supported, e.g. * supported_qpts \|= 1 << IB_QPT_UD / __u32 supported_qpts; }; struct mlx5_ib_rss_caps { __aligned_u64 rx_hash_fields_mask; / enum mlx5_rx_hash_fields / __u8 rx_hash_function; / enum mlx5_rx_hash_function_flags / __u8 reserved[7]; }; enum mlx5_ib_cqe_comp_res_format { MLX5_IB_CQE_RES_FORMAT_HASH = 1 << 0, MLX5_IB_CQE_RES_FORMAT_CSUM = 1 << 1, MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX = 1 << 2, }; struct mlx5_ib_cqe_comp_caps { __u32 max_num; __u32 supported_format; / enum mlx5_ib_cqe_comp_res_format / }; enum mlx5_ib_packet_pacing_cap_flags { MLX5_IB_PP_SUPPORT_BURST = 1 << 0, }; struct mlx5_packet_pacing_caps { __u32 qp_rate_limit_min; __u32 qp_rate_limit_max; / In kpbs / / Corresponding bit will be set if qp type from * 'enum ib_qp_type' is supported, e.g. * supported_qpts \|= 1 << IB_QPT_RAW_PACKET / __u32 supported_qpts; __u8 cap_flags; / enum mlx5_ib_packet_pacing_cap_flags / __u8 reserved[3]; }; enum mlx5_ib_mpw_caps { MPW_RESERVED = 1 << 0, MLX5_IB_ALLOW_MPW = 1 << 1, MLX5_IB_SUPPORT_EMPW = 1 << 2, }; enum mlx5_ib_sw_parsing_offloads { MLX5_IB_SW_PARSING = 1 << 0, MLX5_IB_SW_PARSING_CSUM = 1 << 1, MLX5_IB_SW_PARSING_LSO = 1 << 2, }; struct mlx5_ib_sw_parsing_caps { __u32 sw_parsing_offloads; / enum mlx5_ib_sw_parsing_offloads / / Corresponding bit will be set if qp type from * 'enum ib_qp_type' is supported, e.g. * supported_qpts \|= 1 << IB_QPT_RAW_PACKET / __u32 supported_qpts; }; struct mlx5_ib_striding_rq_caps { __u32 min_single_stride_log_num_of_bytes; __u32 max_single_stride_log_num_of_bytes; __u32 min_single_wqe_log_num_of_strides; __u32 max_single_wqe_log_num_of_strides; / Corresponding bit will be set if qp type from * 'enum ib_qp_type' is supported, e.g. * supported_qpts \|= 1 << IB_QPT_RAW_PACKET / __u32 supported_qpts; __u32 reserved; }; struct mlx5_ib_dci_streams_caps { __u8 max_log_num_concurent; __u8 max_log_num_errored; }; enum mlx5_ib_query_dev_resp_flags { / Support 128B CQE compression / MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP = 1 << 0, MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD = 1 << 1, MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE = 1 << 2, MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT = 1 << 3, MLX5_IB_QUERY_DEV_RESP_FLAGS_OOO_DP = 1 << 4, }; enum mlx5_ib_tunnel_offloads { MLX5_IB_TUNNELED_OFFLOADS_VXLAN = 1 << 0, MLX5_IB_TUNNELED_OFFLOADS_GRE = 1 << 1, MLX5_IB_TUNNELED_OFFLOADS_GENEVE = 1 << 2, MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE = 1 << 3, MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP = 1 << 4, }; struct mlx5_ib_query_device_resp { __u32 comp_mask; __u32 response_length; struct mlx5_ib_tso_caps tso_caps; struct mlx5_ib_rss_caps rss_caps; struct mlx5_ib_cqe_comp_caps cqe_comp_caps; struct mlx5_packet_pacing_caps packet_pacing_caps; __u32 mlx5_ib_support_multi_pkt_send_wqes; __u32 flags; / Use enum mlx5_ib_query_dev_resp_flags / struct mlx5_ib_sw_parsing_caps sw_parsing_caps; struct mlx5_ib_striding_rq_caps striding_rq_caps; __u32 tunnel_offloads_caps; / enum mlx5_ib_tunnel_offloads / struct mlx5_ib_dci_streams_caps dci_streams_caps; __u16 reserved; struct mlx5_ib_uapi_reg reg_c0; }; enum mlx5_ib_create_cq_flags { MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD = 1 << 0, MLX5_IB_CREATE_CQ_FLAGS_UAR_PAGE_INDEX = 1 << 1, MLX5_IB_CREATE_CQ_FLAGS_REAL_TIME_TS = 1 << 2, }; struct mlx5_ib_create_cq { __aligned_u64 buf_addr; __aligned_u64 db_addr; __u32 cqe_size; __u8 cqe_comp_en; __u8 cqe_comp_res_format; __u16 flags; __u16 uar_page_index; __u16 reserved0; __u32 reserved1; }; struct mlx5_ib_create_cq_resp { __u32 cqn; __u32 reserved; }; struct mlx5_ib_resize_cq { __aligned_u64 buf_addr; __u16 cqe_size; __u16 reserved0; __u32 reserved1; }; struct mlx5_ib_create_srq { __aligned_u64 buf_addr; __aligned_u64 db_addr; __u32 flags; __u32 reserved0; / explicit padding (optional on i386) / __u32 uidx; __u32 reserved1; }; struct mlx5_ib_create_srq_resp { __u32 srqn; __u32 reserved; }; struct mlx5_ib_create_qp_dci_streams { __u8 log_num_concurent; __u8 log_num_errored; }; struct mlx5_ib_create_qp { __aligned_u64 buf_addr; __aligned_u64 db_addr; __u32 sq_wqe_count; __u32 rq_wqe_count; __u32 rq_wqe_shift; __u32 flags; __u32 uidx; __u32 bfreg_index; union { __aligned_u64 sq_buf_addr; __aligned_u64 access_key; }; __u32 ece_options; struct mlx5_ib_create_qp_dci_streams dci_streams; __u16 reserved; }; / RX Hash function flags / enum mlx5_rx_hash_function_flags { MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 0, }; / * RX Hash flags, these flags allows to set which incoming packet's field should * participates in RX Hash. Each flag represent certain packet's field, * when the flag is set the field that is represented by the flag will * participate in RX Hash calculation. * Note: IPV4 and IPV6 flags can't be enabled together on the same QP * and TCP and UDP flags can't be enabled together on the same QP. / enum mlx5_rx_hash_fields { MLX5_RX_HASH_SRC_IPV4 = 1 << 0, MLX5_RX_HASH_DST_IPV4 = 1 << 1, MLX5_RX_HASH_SRC_IPV6 = 1 << 2, MLX5_RX_HASH_DST_IPV6 = 1 << 3, MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4, MLX5_RX_HASH_DST_PORT_TCP = 1 << 5, MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6, MLX5_RX_HASH_DST_PORT_UDP = 1 << 7, MLX5_RX_HASH_IPSEC_SPI = 1 << 8, / Save bits for future fields / MLX5_RX_HASH_INNER = (1UL << 31), }; struct mlx5_ib_create_qp_rss { __aligned_u64 rx_hash_fields_mask; / enum mlx5_rx_hash_fields / __u8 rx_hash_function; / enum mlx5_rx_hash_function_flags / __u8 rx_key_len; / valid only for Toeplitz / __u8 reserved[6]; __u8 rx_hash_key[128]; / valid only for Toeplitz / __u32 comp_mask; __u32 flags; }; enum mlx5_ib_create_qp_resp_mask { MLX5_IB_CREATE_QP_RESP_MASK_TIRN = 1UL << 0, MLX5_IB_CREATE_QP_RESP_MASK_TISN = 1UL << 1, MLX5_IB_CREATE_QP_RESP_MASK_RQN = 1UL << 2, MLX5_IB_CREATE_QP_RESP_MASK_SQN = 1UL << 3, MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR = 1UL << 4, }; struct mlx5_ib_create_qp_resp { __u32 bfreg_index; __u32 ece_options; __u32 comp_mask; __u32 tirn; __u32 tisn; __u32 rqn; __u32 sqn; __u32 reserved1; __u64 tir_icm_addr; }; struct mlx5_ib_alloc_mw { __u32 comp_mask; __u8 num_klms; __u8 reserved1; __u16 reserved2; }; enum mlx5_ib_create_wq_mask { MLX5_IB_CREATE_WQ_STRIDING_RQ = (1 << 0), }; struct mlx5_ib_create_wq { __aligned_u64 buf_addr; __aligned_u64 db_addr; __u32 rq_wqe_count; __u32 rq_wqe_shift; __u32 user_index; __u32 flags; __u32 comp_mask; __u32 single_stride_log_num_of_bytes; __u32 single_wqe_log_num_of_strides; __u32 two_byte_shift_en; }; struct mlx5_ib_create_ah_resp { __u32 response_length; __u8 dmac[ETH_ALEN]; __u8 reserved[6]; }; struct mlx5_ib_burst_info { __u32 max_burst_sz; __u16 typical_pkt_sz; __u16 reserved; }; enum mlx5_ib_modify_qp_mask { MLX5_IB_MODIFY_QP_OOO_DP = 1 << 0, }; struct mlx5_ib_modify_qp { __u32 comp_mask; struct mlx5_ib_burst_info burst_info; __u32 ece_options; }; struct mlx5_ib_modify_qp_resp { __u32 response_length; __u32 dctn; __u32 ece_options; __u32 reserved; }; struct mlx5_ib_create_wq_resp { __u32 response_length; __u32 reserved; }; struct mlx5_ib_create_rwq_ind_tbl_resp { __u32 response_length; __u32 reserved; }; struct mlx5_ib_modify_wq { __u32 comp_mask; __u32 reserved; }; struct mlx5_ib_clock_info { __u32 sign; __u32 resv; __aligned_u64 nsec; __aligned_u64 cycles; __aligned_u64 frac; __u32 mult; __u32 shift; __aligned_u64 mask; __aligned_u64 overflow_period; }; enum mlx5_ib_mmap_cmd { MLX5_IB_MMAP_REGULAR_PAGE = 0, MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES = 1, MLX5_IB_MMAP_WC_PAGE = 2, MLX5_IB_MMAP_NC_PAGE = 3, / 5 is chosen in order to be compatible with old versions of libmlx5 / MLX5_IB_MMAP_CORE_CLOCK = 5, MLX5_IB_MMAP_ALLOC_WC = 6, MLX5_IB_MMAP_CLOCK_INFO = 7, MLX5_IB_MMAP_DEVICE_MEM = 8, }; enum { MLX5_IB_CLOCK_INFO_KERNEL_UPDATING = 1, }; / Bit indexes for the mlx5_alloc_ucontext_resp.clock_info_versions bitmap / enum { MLX5_IB_CLOCK_INFO_V1 = 0, }; struct mlx5_ib_flow_counters_desc { __u32 description; __u32 index; }; struct mlx5_ib_flow_counters_data { RDMA_UAPI_PTR(struct mlx5_ib_flow_counters_desc , counters_data); __u32 ncounters; __u32 reserved; }; struct mlx5_ib_create_flow { __u32 ncounters_data; __u32 reserved; /* * Following are counters data based on ncounters_data, each * entry in the data[] should match a corresponding counter object * that was pointed by a counters spec upon the flow creation / struct mlx5_ib_flow_counters_data data[]; }; #endif / MLX5_ABI_USER_H */	13.73 KB	2026-03-24 10:01
📄 mlx5_user_ioctl_cmds.h /* * Copyright (c) 2018, Mellanox Technologies inc. All rights reserved. * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU * General Public License (GPL) Version 2, available from the file * COPYING in the main directory of this source tree, or the * OpenIB.org BSD license below: * * Redistribution and use in source and binary forms, with or * without modification, are permitted provided that the following * conditions are met: * * - Redistributions of source code must retain the above * copyright notice, this list of conditions and the following * disclaimer. * * - Redistributions in binary form must reproduce the above * copyright notice, this list of conditions and the following * disclaimer in the documentation and/or other materials * provided with the distribution. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. / #ifndef MLX5_USER_IOCTL_CMDS_H #define MLX5_USER_IOCTL_CMDS_H #include <linux/types.h> #include <rdma/ib_user_ioctl_cmds.h> enum mlx5_ib_create_flow_action_attrs { / This attribute belong to the driver namespace */ MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS = (1U << UVERBS_ID_NS_SHIFT), }; enum mlx5_ib_dm_methods { MLX5_IB_METHOD_DM_MAP_OP_ADDR = (1U << UVERBS_ID_NS_SHIFT), MLX5_IB_METHOD_DM_QUERY, }; enum mlx5_ib_dm_map_op_addr_attrs { MLX5_IB_ATTR_DM_MAP_OP_ADDR_REQ_HANDLE = (1U << UVERBS_ID_NS_SHIFT), MLX5_IB_ATTR_DM_MAP_OP_ADDR_REQ_OP, MLX5_IB_ATTR_DM_MAP_OP_ADDR_RESP_START_OFFSET, MLX5_IB_ATTR_DM_MAP_OP_ADDR_RESP_PAGE_INDEX, }; enum mlx5_ib_query_dm_attrs { MLX5_IB_ATTR_QUERY_DM_REQ_HANDLE = (1U << UVERBS_ID_NS_SHIFT), MLX5_IB_ATTR_QUERY_DM_RESP_START_OFFSET, MLX5_IB_ATTR_QUERY_DM_RESP_PAGE_INDEX, MLX5_IB_ATTR_QUERY_DM_RESP_LENGTH, }; enum mlx5_ib_alloc_dm_attrs { MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET = (1U << UVERBS_ID_NS_SHIFT), MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX, MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE, }; enum mlx5_ib_devx_methods { MLX5_IB_METHOD_DEVX_OTHER = (1U << UVERBS_ID_NS_SHIFT), MLX5_IB_METHOD_DEVX_QUERY_UAR, MLX5_IB_METHOD_DEVX_QUERY_EQN, MLX5_IB_METHOD_DEVX_SUBSCRIBE_EVENT, }; enum mlx5_ib_devx_other_attrs { MLX5_IB_ATTR_DEVX_OTHER_CMD_IN = (1U << UVERBS_ID_NS_SHIFT), MLX5_IB_ATTR_DEVX_OTHER_CMD_OUT, }; enum mlx5_ib_devx_obj_create_attrs { MLX5_IB_ATTR_DEVX_OBJ_CREATE_HANDLE = (1U << UVERBS_ID_NS_SHIFT), MLX5_IB_ATTR_DEVX_OBJ_CREATE_CMD_IN, MLX5_IB_ATTR_DEVX_OBJ_CREATE_CMD_OUT, }; enum mlx5_ib_devx_query_uar_attrs { MLX5_IB_ATTR_DEVX_QUERY_UAR_USER_IDX = (1U << UVERBS_ID_NS_SHIFT), MLX5_IB_ATTR_DEVX_QUERY_UAR_DEV_IDX, }; enum mlx5_ib_devx_obj_destroy_attrs { MLX5_IB_ATTR_DEVX_OBJ_DESTROY_HANDLE = (1U << UVERBS_ID_NS_SHIFT), }; enum mlx5_ib_devx_obj_modify_attrs { MLX5_IB_ATTR_DEVX_OBJ_MODIFY_HANDLE = (1U << UVERBS_ID_NS_SHIFT), MLX5_IB_ATTR_DEVX_OBJ_MODIFY_CMD_IN, MLX5_IB_ATTR_DEVX_OBJ_MODIFY_CMD_OUT, }; enum mlx5_ib_devx_obj_query_attrs { MLX5_IB_ATTR_DEVX_OBJ_QUERY_HANDLE = (1U << UVERBS_ID_NS_SHIFT), MLX5_IB_ATTR_DEVX_OBJ_QUERY_CMD_IN, MLX5_IB_ATTR_DEVX_OBJ_QUERY_CMD_OUT, }; enum mlx5_ib_devx_obj_query_async_attrs { MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_HANDLE = (1U << UVERBS_ID_NS_SHIFT), MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_CMD_IN, MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_FD, MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_WR_ID, MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_OUT_LEN, }; enum mlx5_ib_devx_subscribe_event_attrs { MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_FD_HANDLE = (1U << UVERBS_ID_NS_SHIFT), MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_OBJ_HANDLE, MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_TYPE_NUM_LIST, MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_FD_NUM, MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_COOKIE, }; enum mlx5_ib_devx_query_eqn_attrs { MLX5_IB_ATTR_DEVX_QUERY_EQN_USER_VEC = (1U << UVERBS_ID_NS_SHIFT), MLX5_IB_ATTR_DEVX_QUERY_EQN_DEV_EQN, }; enum mlx5_ib_devx_obj_methods { MLX5_IB_METHOD_DEVX_OBJ_CREATE = (1U << UVERBS_ID_NS_SHIFT), MLX5_IB_METHOD_DEVX_OBJ_DESTROY, MLX5_IB_METHOD_DEVX_OBJ_MODIFY, MLX5_IB_METHOD_DEVX_OBJ_QUERY, MLX5_IB_METHOD_DEVX_OBJ_ASYNC_QUERY, }; enum mlx5_ib_var_alloc_attrs { MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE = (1U << UVERBS_ID_NS_SHIFT), MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, }; enum mlx5_ib_var_obj_destroy_attrs { MLX5_IB_ATTR_VAR_OBJ_DESTROY_HANDLE = (1U << UVERBS_ID_NS_SHIFT), }; enum mlx5_ib_var_obj_methods { MLX5_IB_METHOD_VAR_OBJ_ALLOC = (1U << UVERBS_ID_NS_SHIFT), MLX5_IB_METHOD_VAR_OBJ_DESTROY, }; enum mlx5_ib_uar_alloc_attrs { MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE = (1U << UVERBS_ID_NS_SHIFT), MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, }; enum mlx5_ib_uar_obj_destroy_attrs { MLX5_IB_ATTR_UAR_OBJ_DESTROY_HANDLE = (1U << UVERBS_ID_NS_SHIFT), }; enum mlx5_ib_uar_obj_methods { MLX5_IB_METHOD_UAR_OBJ_ALLOC = (1U << UVERBS_ID_NS_SHIFT), MLX5_IB_METHOD_UAR_OBJ_DESTROY, }; enum mlx5_ib_devx_umem_reg_attrs { MLX5_IB_ATTR_DEVX_UMEM_REG_HANDLE = (1U << UVERBS_ID_NS_SHIFT), MLX5_IB_ATTR_DEVX_UMEM_REG_ADDR, MLX5_IB_ATTR_DEVX_UMEM_REG_LEN, MLX5_IB_ATTR_DEVX_UMEM_REG_ACCESS, MLX5_IB_ATTR_DEVX_UMEM_REG_OUT_ID, MLX5_IB_ATTR_DEVX_UMEM_REG_PGSZ_BITMAP, MLX5_IB_ATTR_DEVX_UMEM_REG_DMABUF_FD, }; enum mlx5_ib_devx_umem_dereg_attrs { MLX5_IB_ATTR_DEVX_UMEM_DEREG_HANDLE = (1U << UVERBS_ID_NS_SHIFT), }; enum mlx5_ib_pp_obj_methods { MLX5_IB_METHOD_PP_OBJ_ALLOC = (1U << UVERBS_ID_NS_SHIFT), MLX5_IB_METHOD_PP_OBJ_DESTROY, }; enum mlx5_ib_pp_alloc_attrs { MLX5_IB_ATTR_PP_OBJ_ALLOC_HANDLE = (1U << UVERBS_ID_NS_SHIFT), MLX5_IB_ATTR_PP_OBJ_ALLOC_CTX, MLX5_IB_ATTR_PP_OBJ_ALLOC_FLAGS, MLX5_IB_ATTR_PP_OBJ_ALLOC_INDEX, }; enum mlx5_ib_pp_obj_destroy_attrs { MLX5_IB_ATTR_PP_OBJ_DESTROY_HANDLE = (1U << UVERBS_ID_NS_SHIFT), }; enum mlx5_ib_devx_umem_methods { MLX5_IB_METHOD_DEVX_UMEM_REG = (1U << UVERBS_ID_NS_SHIFT), MLX5_IB_METHOD_DEVX_UMEM_DEREG, }; enum mlx5_ib_devx_async_cmd_fd_alloc_attrs { MLX5_IB_ATTR_DEVX_ASYNC_CMD_FD_ALLOC_HANDLE = (1U << UVERBS_ID_NS_SHIFT), }; enum mlx5_ib_devx_async_event_fd_alloc_attrs { MLX5_IB_ATTR_DEVX_ASYNC_EVENT_FD_ALLOC_HANDLE = (1U << UVERBS_ID_NS_SHIFT), MLX5_IB_ATTR_DEVX_ASYNC_EVENT_FD_ALLOC_FLAGS, }; enum mlx5_ib_devx_async_cmd_fd_methods { MLX5_IB_METHOD_DEVX_ASYNC_CMD_FD_ALLOC = (1U << UVERBS_ID_NS_SHIFT), }; enum mlx5_ib_devx_async_event_fd_methods { MLX5_IB_METHOD_DEVX_ASYNC_EVENT_FD_ALLOC = (1U << UVERBS_ID_NS_SHIFT), }; enum mlx5_ib_objects { MLX5_IB_OBJECT_DEVX = (1U << UVERBS_ID_NS_SHIFT), MLX5_IB_OBJECT_DEVX_OBJ, MLX5_IB_OBJECT_DEVX_UMEM, MLX5_IB_OBJECT_FLOW_MATCHER, MLX5_IB_OBJECT_DEVX_ASYNC_CMD_FD, MLX5_IB_OBJECT_DEVX_ASYNC_EVENT_FD, MLX5_IB_OBJECT_VAR, MLX5_IB_OBJECT_PP, MLX5_IB_OBJECT_UAR, MLX5_IB_OBJECT_STEERING_ANCHOR, }; enum mlx5_ib_flow_matcher_create_attrs { MLX5_IB_ATTR_FLOW_MATCHER_CREATE_HANDLE = (1U << UVERBS_ID_NS_SHIFT), MLX5_IB_ATTR_FLOW_MATCHER_MATCH_MASK, MLX5_IB_ATTR_FLOW_MATCHER_FLOW_TYPE, MLX5_IB_ATTR_FLOW_MATCHER_MATCH_CRITERIA, MLX5_IB_ATTR_FLOW_MATCHER_FLOW_FLAGS, MLX5_IB_ATTR_FLOW_MATCHER_FT_TYPE, MLX5_IB_ATTR_FLOW_MATCHER_IB_PORT, }; enum mlx5_ib_flow_matcher_destroy_attrs { MLX5_IB_ATTR_FLOW_MATCHER_DESTROY_HANDLE = (1U << UVERBS_ID_NS_SHIFT), }; enum mlx5_ib_flow_matcher_methods { MLX5_IB_METHOD_FLOW_MATCHER_CREATE = (1U << UVERBS_ID_NS_SHIFT), MLX5_IB_METHOD_FLOW_MATCHER_DESTROY, }; enum mlx5_ib_flow_steering_anchor_create_attrs { MLX5_IB_ATTR_STEERING_ANCHOR_CREATE_HANDLE = (1U << UVERBS_ID_NS_SHIFT), MLX5_IB_ATTR_STEERING_ANCHOR_FT_TYPE, MLX5_IB_ATTR_STEERING_ANCHOR_PRIORITY, MLX5_IB_ATTR_STEERING_ANCHOR_FT_ID, }; enum mlx5_ib_flow_steering_anchor_destroy_attrs { MLX5_IB_ATTR_STEERING_ANCHOR_DESTROY_HANDLE = (1U << UVERBS_ID_NS_SHIFT), }; enum mlx5_ib_steering_anchor_methods { MLX5_IB_METHOD_STEERING_ANCHOR_CREATE = (1U << UVERBS_ID_NS_SHIFT), MLX5_IB_METHOD_STEERING_ANCHOR_DESTROY, }; enum mlx5_ib_device_query_context_attrs { MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX = (1U << UVERBS_ID_NS_SHIFT), }; enum mlx5_ib_create_cq_attrs { MLX5_IB_ATTR_CREATE_CQ_UAR_INDEX = UVERBS_ID_DRIVER_NS_WITH_UHW, }; enum mlx5_ib_reg_dmabuf_mr_attrs { MLX5_IB_ATTR_REG_DMABUF_MR_ACCESS_FLAGS = (1U << UVERBS_ID_NS_SHIFT), }; #define MLX5_IB_DW_MATCH_PARAM 0xA0 struct mlx5_ib_match_params { __u32 match_params[MLX5_IB_DW_MATCH_PARAM]; }; enum mlx5_ib_flow_type { MLX5_IB_FLOW_TYPE_NORMAL, MLX5_IB_FLOW_TYPE_SNIFFER, MLX5_IB_FLOW_TYPE_ALL_DEFAULT, MLX5_IB_FLOW_TYPE_MC_DEFAULT, }; enum mlx5_ib_create_flow_flags { MLX5_IB_ATTR_CREATE_FLOW_FLAGS_DEFAULT_MISS = 1 << 0, MLX5_IB_ATTR_CREATE_FLOW_FLAGS_DROP = 1 << 1, }; enum mlx5_ib_create_flow_attrs { MLX5_IB_ATTR_CREATE_FLOW_HANDLE = (1U << UVERBS_ID_NS_SHIFT), MLX5_IB_ATTR_CREATE_FLOW_MATCH_VALUE, MLX5_IB_ATTR_CREATE_FLOW_DEST_QP, MLX5_IB_ATTR_CREATE_FLOW_DEST_DEVX, MLX5_IB_ATTR_CREATE_FLOW_MATCHER, MLX5_IB_ATTR_CREATE_FLOW_ARR_FLOW_ACTIONS, MLX5_IB_ATTR_CREATE_FLOW_TAG, MLX5_IB_ATTR_CREATE_FLOW_ARR_COUNTERS_DEVX, MLX5_IB_ATTR_CREATE_FLOW_ARR_COUNTERS_DEVX_OFFSET, MLX5_IB_ATTR_CREATE_FLOW_FLAGS, }; enum mlx5_ib_destroy_flow_attrs { MLX5_IB_ATTR_DESTROY_FLOW_HANDLE = (1U << UVERBS_ID_NS_SHIFT), }; enum mlx5_ib_flow_methods { MLX5_IB_METHOD_CREATE_FLOW = (1U << UVERBS_ID_NS_SHIFT), MLX5_IB_METHOD_DESTROY_FLOW, }; enum mlx5_ib_flow_action_methods { MLX5_IB_METHOD_FLOW_ACTION_CREATE_MODIFY_HEADER = (1U << UVERBS_ID_NS_SHIFT), MLX5_IB_METHOD_FLOW_ACTION_CREATE_PACKET_REFORMAT, }; enum mlx5_ib_create_flow_action_create_modify_header_attrs { MLX5_IB_ATTR_CREATE_MODIFY_HEADER_HANDLE = (1U << UVERBS_ID_NS_SHIFT), MLX5_IB_ATTR_CREATE_MODIFY_HEADER_ACTIONS_PRM, MLX5_IB_ATTR_CREATE_MODIFY_HEADER_FT_TYPE, }; enum mlx5_ib_create_flow_action_create_packet_reformat_attrs { MLX5_IB_ATTR_CREATE_PACKET_REFORMAT_HANDLE = (1U << UVERBS_ID_NS_SHIFT), MLX5_IB_ATTR_CREATE_PACKET_REFORMAT_TYPE, MLX5_IB_ATTR_CREATE_PACKET_REFORMAT_FT_TYPE, MLX5_IB_ATTR_CREATE_PACKET_REFORMAT_DATA_BUF, }; enum mlx5_ib_query_pd_attrs { MLX5_IB_ATTR_QUERY_PD_HANDLE = (1U << UVERBS_ID_NS_SHIFT), MLX5_IB_ATTR_QUERY_PD_RESP_PDN, }; enum mlx5_ib_pd_methods { MLX5_IB_METHOD_PD_QUERY = (1U << UVERBS_ID_NS_SHIFT), }; enum mlx5_ib_device_methods { MLX5_IB_METHOD_QUERY_PORT = (1U << UVERBS_ID_NS_SHIFT), MLX5_IB_METHOD_GET_DATA_DIRECT_SYSFS_PATH, }; enum mlx5_ib_query_port_attrs { MLX5_IB_ATTR_QUERY_PORT_PORT_NUM = (1U << UVERBS_ID_NS_SHIFT), MLX5_IB_ATTR_QUERY_PORT, }; enum mlx5_ib_get_data_direct_sysfs_path_attrs { MLX5_IB_ATTR_GET_DATA_DIRECT_SYSFS_PATH = (1U << UVERBS_ID_NS_SHIFT), }; #endif	10.94 KB	2026-03-24 10:01
📄 mlx5_user_ioctl_verbs.h /* * Copyright (c) 2018, Mellanox Technologies inc. All rights reserved. * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU * General Public License (GPL) Version 2, available from the file * COPYING in the main directory of this source tree, or the * OpenIB.org BSD license below: * * Redistribution and use in source and binary forms, with or * without modification, are permitted provided that the following * conditions are met: * * - Redistributions of source code must retain the above * copyright notice, this list of conditions and the following * disclaimer. * * - Redistributions in binary form must reproduce the above * copyright notice, this list of conditions and the following * disclaimer in the documentation and/or other materials * provided with the distribution. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ #ifndef MLX5_USER_IOCTL_VERBS_H #define MLX5_USER_IOCTL_VERBS_H #include <linux/types.h> enum mlx5_ib_uapi_flow_action_flags { MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA = 1 << 0, }; enum mlx5_ib_uapi_flow_table_type { MLX5_IB_UAPI_FLOW_TABLE_TYPE_NIC_RX = 0x0, MLX5_IB_UAPI_FLOW_TABLE_TYPE_NIC_TX = 0x1, MLX5_IB_UAPI_FLOW_TABLE_TYPE_FDB = 0x2, MLX5_IB_UAPI_FLOW_TABLE_TYPE_RDMA_RX = 0x3, MLX5_IB_UAPI_FLOW_TABLE_TYPE_RDMA_TX = 0x4, MLX5_IB_UAPI_FLOW_TABLE_TYPE_RDMA_TRANSPORT_RX = 0x5, MLX5_IB_UAPI_FLOW_TABLE_TYPE_RDMA_TRANSPORT_TX = 0x6, }; enum mlx5_ib_uapi_flow_action_packet_reformat_type { MLX5_IB_UAPI_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 = 0x0, MLX5_IB_UAPI_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x1, MLX5_IB_UAPI_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x2, MLX5_IB_UAPI_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x3, }; enum mlx5_ib_uapi_reg_dmabuf_flags { MLX5_IB_UAPI_REG_DMABUF_ACCESS_DATA_DIRECT = 1 << 0, }; struct mlx5_ib_uapi_devx_async_cmd_hdr { __aligned_u64 wr_id; __u8 out_data[]; }; enum mlx5_ib_uapi_dm_type { MLX5_IB_UAPI_DM_TYPE_MEMIC, MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM, MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM, MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_PATTERN_SW_ICM, MLX5_IB_UAPI_DM_TYPE_ENCAP_SW_ICM, }; enum mlx5_ib_uapi_devx_create_event_channel_flags { MLX5_IB_UAPI_DEVX_CR_EV_CH_FLAGS_OMIT_DATA = 1 << 0, }; struct mlx5_ib_uapi_devx_async_event_hdr { __aligned_u64 cookie; __u8 out_data[]; }; enum mlx5_ib_uapi_pp_alloc_flags { MLX5_IB_UAPI_PP_ALLOC_FLAGS_DEDICATED_INDEX = 1 << 0, }; enum mlx5_ib_uapi_uar_alloc_type { MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF = 0x0, MLX5_IB_UAPI_UAR_ALLOC_TYPE_NC = 0x1, }; enum mlx5_ib_uapi_query_port_flags { MLX5_IB_UAPI_QUERY_PORT_VPORT = 1 << 0, MLX5_IB_UAPI_QUERY_PORT_VPORT_VHCA_ID = 1 << 1, MLX5_IB_UAPI_QUERY_PORT_VPORT_STEERING_ICM_RX = 1 << 2, MLX5_IB_UAPI_QUERY_PORT_VPORT_STEERING_ICM_TX = 1 << 3, MLX5_IB_UAPI_QUERY_PORT_VPORT_REG_C0 = 1 << 4, MLX5_IB_UAPI_QUERY_PORT_ESW_OWNER_VHCA_ID = 1 << 5, }; struct mlx5_ib_uapi_reg { __u32 value; __u32 mask; }; struct mlx5_ib_uapi_query_port { __aligned_u64 flags; __u16 vport; __u16 vport_vhca_id; __u16 esw_owner_vhca_id; __u16 rsvd0; __aligned_u64 vport_steering_icm_rx; __aligned_u64 vport_steering_icm_tx; struct mlx5_ib_uapi_reg reg_c0; }; #endif	3.73 KB	2026-03-24 10:01
📄 mthca-abi.h /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) / / * Copyright (c) 2005 Topspin Communications. All rights reserved. * Copyright (c) 2005, 2006 Cisco Systems. All rights reserved. * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU * General Public License (GPL) Version 2, available from the file * COPYING in the main directory of this source tree, or the * OpenIB.org BSD license below: * * Redistribution and use in source and binary forms, with or * without modification, are permitted provided that the following * conditions are met: * * - Redistributions of source code must retain the above * copyright notice, this list of conditions and the following * disclaimer. * * - Redistributions in binary form must reproduce the above * copyright notice, this list of conditions and the following * disclaimer in the documentation and/or other materials * provided with the distribution. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. / #ifndef MTHCA_ABI_USER_H #define MTHCA_ABI_USER_H #include <linux/types.h> / * Increment this value if any changes that break userspace ABI * compatibility are made. / #define MTHCA_UVERBS_ABI_VERSION 1 / * Make sure that all structs defined in this file remain laid out so * that they pack the same way on 32-bit and 64-bit architectures (to * avoid incompatibility between 32-bit userspace and 64-bit kernels). * In particular do not use pointer types -- pass pointers in __u64 * instead. / struct mthca_alloc_ucontext_resp { __u32 qp_tab_size; __u32 uarc_size; }; struct mthca_alloc_pd_resp { __u32 pdn; __u32 reserved; }; / * Mark the memory region with a DMA attribute that causes * in-flight DMA to be flushed when the region is written to: / #define MTHCA_MR_DMASYNC 0x1 struct mthca_reg_mr { __u32 mr_attrs; __u32 reserved; }; struct mthca_create_cq { __u32 lkey; __u32 pdn; __aligned_u64 arm_db_page; __aligned_u64 set_db_page; __u32 arm_db_index; __u32 set_db_index; }; struct mthca_create_cq_resp { __u32 cqn; __u32 reserved; }; struct mthca_resize_cq { __u32 lkey; __u32 reserved; }; struct mthca_create_srq { __u32 lkey; __u32 db_index; __aligned_u64 db_page; }; struct mthca_create_srq_resp { __u32 srqn; __u32 reserved; }; struct mthca_create_qp { __u32 lkey; __u32 reserved; __aligned_u64 sq_db_page; __aligned_u64 rq_db_page; __u32 sq_db_index; __u32 rq_db_index; }; #endif / MTHCA_ABI_USER_H */	2.98 KB	2026-03-24 10:01
📄 ocrdma-abi.h /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) / / This file is part of the Emulex RoCE Device Driver for * RoCE (RDMA over Converged Ethernet) adapters. * Copyright (C) 2012-2015 Emulex. All rights reserved. * EMULEX and SLI are trademarks of Emulex. * www.emulex.com * * This software is available to you under a choice of one of two licenses. * You may choose to be licensed under the terms of the GNU General Public * License (GPL) Version 2, available from the file COPYING in the main * directory of this source tree, or the BSD license below: * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * - Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * * - Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Contact Information: * linux-drivers@emulex.com * * Emulex * 3333 Susan Street * Costa Mesa, CA 92626 / #ifndef OCRDMA_ABI_USER_H #define OCRDMA_ABI_USER_H #include <linux/types.h> #define OCRDMA_ABI_VERSION 2 #define OCRDMA_BE_ROCE_ABI_VERSION 1 / user kernel communication data structures. / struct ocrdma_alloc_ucontext_resp { __u32 dev_id; __u32 wqe_size; __u32 max_inline_data; __u32 dpp_wqe_size; __aligned_u64 ah_tbl_page; __u32 ah_tbl_len; __u32 rqe_size; __u8 fw_ver[32]; / for future use/new features in progress / __aligned_u64 rsvd1; __aligned_u64 rsvd2; }; struct ocrdma_alloc_pd_ureq { __u32 rsvd[2]; }; struct ocrdma_alloc_pd_uresp { __u32 id; __u32 dpp_enabled; __u32 dpp_page_addr_hi; __u32 dpp_page_addr_lo; __u32 rsvd[2]; }; struct ocrdma_create_cq_ureq { __u32 dpp_cq; __u32 rsvd; / pad / }; #define MAX_CQ_PAGES 8 struct ocrdma_create_cq_uresp { __u32 cq_id; __u32 page_size; __u32 num_pages; __u32 max_hw_cqe; __aligned_u64 page_addr[MAX_CQ_PAGES]; __aligned_u64 db_page_addr; __u32 db_page_size; __u32 phase_change; / for future use/new features in progress / __aligned_u64 rsvd1; __aligned_u64 rsvd2; }; #define MAX_QP_PAGES 8 #define MAX_UD_AV_PAGES 8 struct ocrdma_create_qp_ureq { __u8 enable_dpp_cq; __u8 rsvd; __u16 dpp_cq_id; __u32 rsvd1; / pad / }; struct ocrdma_create_qp_uresp { __u16 qp_id; __u16 sq_dbid; __u16 rq_dbid; __u16 resv0; / pad / __u32 sq_page_size; __u32 rq_page_size; __u32 num_sq_pages; __u32 num_rq_pages; __aligned_u64 sq_page_addr[MAX_QP_PAGES]; __aligned_u64 rq_page_addr[MAX_QP_PAGES]; __aligned_u64 db_page_addr; __u32 db_page_size; __u32 dpp_credit; __u32 dpp_offset; __u32 num_wqe_allocated; __u32 num_rqe_allocated; __u32 db_sq_offset; __u32 db_rq_offset; __u32 db_shift; __aligned_u64 rsvd[11]; }; struct ocrdma_create_srq_uresp { __u16 rq_dbid; __u16 resv0; / pad / __u32 resv1; __u32 rq_page_size; __u32 num_rq_pages; __aligned_u64 rq_page_addr[MAX_QP_PAGES]; __aligned_u64 db_page_addr; __u32 db_page_size; __u32 num_rqe_allocated; __u32 db_rq_offset; __u32 db_shift; __aligned_u64 rsvd2; __aligned_u64 rsvd3; }; #endif / OCRDMA_ABI_USER_H */	4.02 KB	2026-03-24 10:01
📄 qedr-abi.h /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) / / QLogic qedr NIC Driver * Copyright (c) 2015-2016 QLogic Corporation * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU * General Public License (GPL) Version 2, available from the file * COPYING in the main directory of this source tree, or the * OpenIB.org BSD license below: * * Redistribution and use in source and binary forms, with or * without modification, are permitted provided that the following * conditions are met: * * - Redistributions of source code must retain the above * copyright notice, this list of conditions and the following * disclaimer. * * - Redistributions in binary form must reproduce the above * copyright notice, this list of conditions and the following * disclaimer in the documentation and /or other materials * provided with the distribution. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. / #ifndef __QEDR_USER_H__ #define __QEDR_USER_H__ #include <linux/types.h> #define QEDR_ABI_VERSION (8) / user kernel communication data structures. / enum qedr_alloc_ucontext_flags { QEDR_ALLOC_UCTX_EDPM_MODE = 1 << 0, QEDR_ALLOC_UCTX_DB_REC = 1 << 1, QEDR_SUPPORT_DPM_SIZES = 1 << 2, }; struct qedr_alloc_ucontext_req { __u32 context_flags; __u32 reserved; }; #define QEDR_LDPM_MAX_SIZE (8192) #define QEDR_EDPM_TRANS_SIZE (64) #define QEDR_EDPM_MAX_SIZE (ROCE_REQ_MAX_INLINE_DATA_SIZE) enum qedr_rdma_dpm_type { QEDR_DPM_TYPE_NONE = 0, QEDR_DPM_TYPE_ROCE_ENHANCED = 1 << 0, QEDR_DPM_TYPE_ROCE_LEGACY = 1 << 1, QEDR_DPM_TYPE_IWARP_LEGACY = 1 << 2, QEDR_DPM_TYPE_ROCE_EDPM_MODE = 1 << 3, QEDR_DPM_SIZES_SET = 1 << 4, }; struct qedr_alloc_ucontext_resp { __aligned_u64 db_pa; __u32 db_size; __u32 max_send_wr; __u32 max_recv_wr; __u32 max_srq_wr; __u32 sges_per_send_wr; __u32 sges_per_recv_wr; __u32 sges_per_srq_wr; __u32 max_cqes; __u8 dpm_flags; __u8 wids_enabled; __u16 wid_count; __u16 ldpm_limit_size; __u8 edpm_trans_size; __u8 reserved; __u16 edpm_limit_size; __u8 padding[6]; }; struct qedr_alloc_pd_ureq { __aligned_u64 rsvd1; }; struct qedr_alloc_pd_uresp { __u32 pd_id; __u32 reserved; }; struct qedr_create_cq_ureq { __aligned_u64 addr; __aligned_u64 len; }; struct qedr_create_cq_uresp { __u32 db_offset; __u16 icid; __u16 reserved; __aligned_u64 db_rec_addr; }; struct qedr_create_qp_ureq { __u32 qp_handle_hi; __u32 qp_handle_lo; / SQ / / user space virtual address of SQ buffer / __aligned_u64 sq_addr; / length of SQ buffer / __aligned_u64 sq_len; / RQ / / user space virtual address of RQ buffer / __aligned_u64 rq_addr; / length of RQ buffer / __aligned_u64 rq_len; }; struct qedr_create_qp_uresp { __u32 qp_id; __u32 atomic_supported; / SQ / __u32 sq_db_offset; __u16 sq_icid; / RQ / __u32 rq_db_offset; __u16 rq_icid; __u32 rq_db2_offset; __u32 reserved; / address of SQ doorbell recovery user entry / __aligned_u64 sq_db_rec_addr; / address of RQ doorbell recovery user entry / __aligned_u64 rq_db_rec_addr; }; struct qedr_create_srq_ureq { / user space virtual address of producer pair / __aligned_u64 prod_pair_addr; / user space virtual address of SRQ buffer / __aligned_u64 srq_addr; / length of SRQ buffer / __aligned_u64 srq_len; }; struct qedr_create_srq_uresp { __u16 srq_id; __u16 reserved0; __u32 reserved1; }; / doorbell recovery entry allocated and populated by userspace doorbelling * entities and mapped to kernel. Kernel uses this to register doorbell * information with doorbell drop recovery mechanism. / struct qedr_user_db_rec { __aligned_u64 db_data; / doorbell data / }; #endif / __QEDR_USER_H__ */	4.21 KB	2026-03-24 10:01
📄 rdma_netlink.h /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note / #ifndef _RDMA_NETLINK_H #define _RDMA_NETLINK_H #include <linux/types.h> enum { RDMA_NL_IWCM = 2, RDMA_NL_RSVD, RDMA_NL_LS, / RDMA Local Services / RDMA_NL_NLDEV, / RDMA device interface / RDMA_NL_NUM_CLIENTS }; enum { RDMA_NL_GROUP_IWPM = 2, RDMA_NL_GROUP_LS, RDMA_NL_GROUP_NOTIFY, RDMA_NL_NUM_GROUPS }; #define RDMA_NL_GET_CLIENT(type) ((type & (((1 << 6) - 1) << 10)) >> 10) #define RDMA_NL_GET_OP(type) (type & ((1 << 10) - 1)) #define RDMA_NL_GET_TYPE(client, op) ((client << 10) + op) / The minimum version that the iwpm kernel supports / #define IWPM_UABI_VERSION_MIN 3 / The latest version that the iwpm kernel supports / #define IWPM_UABI_VERSION 4 / iwarp port mapper message flags / enum { / Do not map the port for this IWPM request / IWPM_FLAGS_NO_PORT_MAP = (1 << 0), }; / iwarp port mapper op-codes / enum { RDMA_NL_IWPM_REG_PID = 0, RDMA_NL_IWPM_ADD_MAPPING, RDMA_NL_IWPM_QUERY_MAPPING, RDMA_NL_IWPM_REMOVE_MAPPING, RDMA_NL_IWPM_REMOTE_INFO, RDMA_NL_IWPM_HANDLE_ERR, RDMA_NL_IWPM_MAPINFO, RDMA_NL_IWPM_MAPINFO_NUM, RDMA_NL_IWPM_HELLO, RDMA_NL_IWPM_NUM_OPS }; enum { IWPM_NLA_REG_PID_UNSPEC = 0, IWPM_NLA_REG_PID_SEQ, IWPM_NLA_REG_IF_NAME, IWPM_NLA_REG_IBDEV_NAME, IWPM_NLA_REG_ULIB_NAME, IWPM_NLA_REG_PID_MAX }; enum { IWPM_NLA_RREG_PID_UNSPEC = 0, IWPM_NLA_RREG_PID_SEQ, IWPM_NLA_RREG_IBDEV_NAME, IWPM_NLA_RREG_ULIB_NAME, IWPM_NLA_RREG_ULIB_VER, IWPM_NLA_RREG_PID_ERR, IWPM_NLA_RREG_PID_MAX }; enum { IWPM_NLA_MANAGE_MAPPING_UNSPEC = 0, IWPM_NLA_MANAGE_MAPPING_SEQ, IWPM_NLA_MANAGE_ADDR, IWPM_NLA_MANAGE_FLAGS, IWPM_NLA_MANAGE_MAPPING_MAX }; enum { IWPM_NLA_RMANAGE_MAPPING_UNSPEC = 0, IWPM_NLA_RMANAGE_MAPPING_SEQ, IWPM_NLA_RMANAGE_ADDR, IWPM_NLA_RMANAGE_MAPPED_LOC_ADDR, / The following maintains bisectability of rdma-core / IWPM_NLA_MANAGE_MAPPED_LOC_ADDR = IWPM_NLA_RMANAGE_MAPPED_LOC_ADDR, IWPM_NLA_RMANAGE_MAPPING_ERR, IWPM_NLA_RMANAGE_MAPPING_MAX }; #define IWPM_NLA_MAPINFO_SEND_MAX 3 #define IWPM_NLA_REMOVE_MAPPING_MAX 3 enum { IWPM_NLA_QUERY_MAPPING_UNSPEC = 0, IWPM_NLA_QUERY_MAPPING_SEQ, IWPM_NLA_QUERY_LOCAL_ADDR, IWPM_NLA_QUERY_REMOTE_ADDR, IWPM_NLA_QUERY_FLAGS, IWPM_NLA_QUERY_MAPPING_MAX, }; enum { IWPM_NLA_RQUERY_MAPPING_UNSPEC = 0, IWPM_NLA_RQUERY_MAPPING_SEQ, IWPM_NLA_RQUERY_LOCAL_ADDR, IWPM_NLA_RQUERY_REMOTE_ADDR, IWPM_NLA_RQUERY_MAPPED_LOC_ADDR, IWPM_NLA_RQUERY_MAPPED_REM_ADDR, IWPM_NLA_RQUERY_MAPPING_ERR, IWPM_NLA_RQUERY_MAPPING_MAX }; enum { IWPM_NLA_MAPINFO_REQ_UNSPEC = 0, IWPM_NLA_MAPINFO_ULIB_NAME, IWPM_NLA_MAPINFO_ULIB_VER, IWPM_NLA_MAPINFO_REQ_MAX }; enum { IWPM_NLA_MAPINFO_UNSPEC = 0, IWPM_NLA_MAPINFO_LOCAL_ADDR, IWPM_NLA_MAPINFO_MAPPED_ADDR, IWPM_NLA_MAPINFO_FLAGS, IWPM_NLA_MAPINFO_MAX }; enum { IWPM_NLA_MAPINFO_NUM_UNSPEC = 0, IWPM_NLA_MAPINFO_SEQ, IWPM_NLA_MAPINFO_SEND_NUM, IWPM_NLA_MAPINFO_ACK_NUM, IWPM_NLA_MAPINFO_NUM_MAX }; enum { IWPM_NLA_ERR_UNSPEC = 0, IWPM_NLA_ERR_SEQ, IWPM_NLA_ERR_CODE, IWPM_NLA_ERR_MAX }; enum { IWPM_NLA_HELLO_UNSPEC = 0, IWPM_NLA_HELLO_ABI_VERSION, IWPM_NLA_HELLO_MAX }; / For RDMA_NLDEV_ATTR_DEV_NODE_TYPE / enum { / IB values map to NodeInfo:NodeType. / RDMA_NODE_IB_CA = 1, RDMA_NODE_IB_SWITCH, RDMA_NODE_IB_ROUTER, RDMA_NODE_RNIC, RDMA_NODE_USNIC, RDMA_NODE_USNIC_UDP, RDMA_NODE_UNSPECIFIED, }; / * Local service operations: * RESOLVE - The client requests the local service to resolve a path. * SET_TIMEOUT - The local service requests the client to set the timeout. * IP_RESOLVE - The client requests the local service to resolve an IP to GID. / enum { RDMA_NL_LS_OP_RESOLVE = 0, RDMA_NL_LS_OP_SET_TIMEOUT, RDMA_NL_LS_OP_IP_RESOLVE, RDMA_NL_LS_NUM_OPS }; / Local service netlink message flags / #define RDMA_NL_LS_F_ERR 0x0100 / Failed response / / * Local service resolve operation family header. * The layout for the resolve operation: * nlmsg header * family header * attributes / / * Local service path use: * Specify how the path(s) will be used. * ALL - For connected CM operation (6 pathrecords) * UNIDIRECTIONAL - For unidirectional UD (1 pathrecord) * GMP - For miscellaneous GMP like operation (at least 1 reversible * pathrecord) / enum { LS_RESOLVE_PATH_USE_ALL = 0, LS_RESOLVE_PATH_USE_UNIDIRECTIONAL, LS_RESOLVE_PATH_USE_GMP, LS_RESOLVE_PATH_USE_MAX }; #define LS_DEVICE_NAME_MAX 64 struct rdma_ls_resolve_header { __u8 device_name[LS_DEVICE_NAME_MAX]; __u8 port_num; __u8 path_use; }; struct rdma_ls_ip_resolve_header { __u32 ifindex; }; / Local service attribute type / #define RDMA_NLA_F_MANDATORY (1 << 13) #define RDMA_NLA_TYPE_MASK (~(NLA_F_NESTED \| NLA_F_NET_BYTEORDER \| \ RDMA_NLA_F_MANDATORY)) / * Local service attributes: * Attr Name Size Byte order * ----------------------------------------------------- * PATH_RECORD struct ib_path_rec_data * TIMEOUT u32 cpu * SERVICE_ID u64 cpu * DGID u8[16] BE * SGID u8[16] BE * TCLASS u8 * PKEY u16 cpu * QOS_CLASS u16 cpu * IPV4 u32 BE * IPV6 u8[16] BE / enum { LS_NLA_TYPE_UNSPEC = 0, LS_NLA_TYPE_PATH_RECORD, LS_NLA_TYPE_TIMEOUT, LS_NLA_TYPE_SERVICE_ID, LS_NLA_TYPE_DGID, LS_NLA_TYPE_SGID, LS_NLA_TYPE_TCLASS, LS_NLA_TYPE_PKEY, LS_NLA_TYPE_QOS_CLASS, LS_NLA_TYPE_IPV4, LS_NLA_TYPE_IPV6, LS_NLA_TYPE_MAX }; / Local service DGID/SGID attribute: big endian / struct rdma_nla_ls_gid { __u8 gid[16]; }; enum rdma_nldev_command { RDMA_NLDEV_CMD_UNSPEC, RDMA_NLDEV_CMD_GET, / can dump / RDMA_NLDEV_CMD_SET, RDMA_NLDEV_CMD_NEWLINK, RDMA_NLDEV_CMD_DELLINK, RDMA_NLDEV_CMD_PORT_GET, / can dump / RDMA_NLDEV_CMD_SYS_GET, RDMA_NLDEV_CMD_SYS_SET, / 8 is free to use / RDMA_NLDEV_CMD_RES_GET = 9, / can dump / RDMA_NLDEV_CMD_RES_QP_GET, / can dump / RDMA_NLDEV_CMD_RES_CM_ID_GET, / can dump / RDMA_NLDEV_CMD_RES_CQ_GET, / can dump / RDMA_NLDEV_CMD_RES_MR_GET, / can dump / RDMA_NLDEV_CMD_RES_PD_GET, / can dump / RDMA_NLDEV_CMD_GET_CHARDEV, RDMA_NLDEV_CMD_STAT_SET, RDMA_NLDEV_CMD_STAT_GET, / can dump / RDMA_NLDEV_CMD_STAT_DEL, RDMA_NLDEV_CMD_RES_QP_GET_RAW, RDMA_NLDEV_CMD_RES_CQ_GET_RAW, RDMA_NLDEV_CMD_RES_MR_GET_RAW, RDMA_NLDEV_CMD_RES_CTX_GET, / can dump / RDMA_NLDEV_CMD_RES_SRQ_GET, / can dump / RDMA_NLDEV_CMD_STAT_GET_STATUS, RDMA_NLDEV_CMD_RES_SRQ_GET_RAW, RDMA_NLDEV_CMD_NEWDEV, RDMA_NLDEV_CMD_DELDEV, RDMA_NLDEV_CMD_MONITOR, RDMA_NLDEV_NUM_OPS }; enum rdma_nldev_print_type { RDMA_NLDEV_PRINT_TYPE_UNSPEC, RDMA_NLDEV_PRINT_TYPE_HEX, }; enum rdma_nldev_attr { / don't change the order or add anything between, this is ABI! / RDMA_NLDEV_ATTR_UNSPEC, / Pad attribute for 64b alignment / RDMA_NLDEV_ATTR_PAD = RDMA_NLDEV_ATTR_UNSPEC, / Identifier for ib_device / RDMA_NLDEV_ATTR_DEV_INDEX, / u32 / RDMA_NLDEV_ATTR_DEV_NAME, / string / / * Device index together with port index are identifiers * for port/link properties. * * For RDMA_NLDEV_CMD_GET commamnd, port index will return number * of available ports in ib_device, while for port specific operations, * it will be real port index as it appears in sysfs. Port index follows * sysfs notation and starts from 1 for the first port. / RDMA_NLDEV_ATTR_PORT_INDEX, / u32 / / * Device and port capabilities * * When used for port info, first 32-bits are CapabilityMask followed by * 16-bit CapabilityMask2. / RDMA_NLDEV_ATTR_CAP_FLAGS, / u64 / / * FW version / RDMA_NLDEV_ATTR_FW_VERSION, / string / / * Node GUID (in host byte order) associated with the RDMA device. / RDMA_NLDEV_ATTR_NODE_GUID, / u64 / / * System image GUID (in host byte order) associated with * this RDMA device and other devices which are part of a * single system. / RDMA_NLDEV_ATTR_SYS_IMAGE_GUID, / u64 / / * Subnet prefix (in host byte order) / RDMA_NLDEV_ATTR_SUBNET_PREFIX, / u64 / / * Local Identifier (LID), * According to IB specification, It is 16-bit address assigned * by the Subnet Manager. Extended to be 32-bit for OmniPath users. / RDMA_NLDEV_ATTR_LID, / u32 / RDMA_NLDEV_ATTR_SM_LID, / u32 / / * LID mask control (LMC) / RDMA_NLDEV_ATTR_LMC, / u8 / RDMA_NLDEV_ATTR_PORT_STATE, / u8 / RDMA_NLDEV_ATTR_PORT_PHYS_STATE, / u8 / RDMA_NLDEV_ATTR_DEV_NODE_TYPE, / u8 / RDMA_NLDEV_ATTR_RES_SUMMARY, / nested table / RDMA_NLDEV_ATTR_RES_SUMMARY_ENTRY, / nested table / RDMA_NLDEV_ATTR_RES_SUMMARY_ENTRY_NAME, / string / RDMA_NLDEV_ATTR_RES_SUMMARY_ENTRY_CURR, / u64 / RDMA_NLDEV_ATTR_RES_QP, / nested table / RDMA_NLDEV_ATTR_RES_QP_ENTRY, / nested table / / * Local QPN / RDMA_NLDEV_ATTR_RES_LQPN, / u32 / / * Remote QPN, * Applicable for RC and UC only IBTA 11.2.5.3 QUERY QUEUE PAIR / RDMA_NLDEV_ATTR_RES_RQPN, / u32 / / * Receive Queue PSN, * Applicable for RC and UC only 11.2.5.3 QUERY QUEUE PAIR / RDMA_NLDEV_ATTR_RES_RQ_PSN, / u32 / / * Send Queue PSN / RDMA_NLDEV_ATTR_RES_SQ_PSN, / u32 / RDMA_NLDEV_ATTR_RES_PATH_MIG_STATE, / u8 / / * QP types as visible to RDMA/core, the reserved QPT * are not exported through this interface. / RDMA_NLDEV_ATTR_RES_TYPE, / u8 / RDMA_NLDEV_ATTR_RES_STATE, / u8 / / * Process ID which created object, * in case of kernel origin, PID won't exist. / RDMA_NLDEV_ATTR_RES_PID, / u32 / / * The name of process created following resource. * It will exist only for kernel objects. * For user created objects, the user is supposed * to read /proc/PID/comm file. / RDMA_NLDEV_ATTR_RES_KERN_NAME, / string / RDMA_NLDEV_ATTR_RES_CM_ID, / nested table / RDMA_NLDEV_ATTR_RES_CM_ID_ENTRY, / nested table / / * rdma_cm_id port space. / RDMA_NLDEV_ATTR_RES_PS, / u32 / / * Source and destination socket addresses / RDMA_NLDEV_ATTR_RES_SRC_ADDR, / __kernel_sockaddr_storage / RDMA_NLDEV_ATTR_RES_DST_ADDR, / __kernel_sockaddr_storage / RDMA_NLDEV_ATTR_RES_CQ, / nested table / RDMA_NLDEV_ATTR_RES_CQ_ENTRY, / nested table / RDMA_NLDEV_ATTR_RES_CQE, / u32 / RDMA_NLDEV_ATTR_RES_USECNT, / u64 / RDMA_NLDEV_ATTR_RES_POLL_CTX, / u8 / RDMA_NLDEV_ATTR_RES_MR, / nested table / RDMA_NLDEV_ATTR_RES_MR_ENTRY, / nested table / RDMA_NLDEV_ATTR_RES_RKEY, / u32 / RDMA_NLDEV_ATTR_RES_LKEY, / u32 / RDMA_NLDEV_ATTR_RES_IOVA, / u64 / RDMA_NLDEV_ATTR_RES_MRLEN, / u64 / RDMA_NLDEV_ATTR_RES_PD, / nested table / RDMA_NLDEV_ATTR_RES_PD_ENTRY, / nested table / RDMA_NLDEV_ATTR_RES_LOCAL_DMA_LKEY, / u32 / RDMA_NLDEV_ATTR_RES_UNSAFE_GLOBAL_RKEY, / u32 / / * Provides logical name and index of netdevice which is * connected to physical port. This information is relevant * for RoCE and iWARP. * * The netdevices which are associated with containers are * supposed to be exported together with GID table once it * will be exposed through the netlink. Because the * associated netdevices are properties of GIDs. / RDMA_NLDEV_ATTR_NDEV_INDEX, / u32 / RDMA_NLDEV_ATTR_NDEV_NAME, / string / / * driver-specific attributes. / RDMA_NLDEV_ATTR_DRIVER, / nested table / RDMA_NLDEV_ATTR_DRIVER_ENTRY, / nested table / RDMA_NLDEV_ATTR_DRIVER_STRING, / string / / * u8 values from enum rdma_nldev_print_type / RDMA_NLDEV_ATTR_DRIVER_PRINT_TYPE, / u8 / RDMA_NLDEV_ATTR_DRIVER_S32, / s32 / RDMA_NLDEV_ATTR_DRIVER_U32, / u32 / RDMA_NLDEV_ATTR_DRIVER_S64, / s64 / RDMA_NLDEV_ATTR_DRIVER_U64, / u64 / / * Indexes to get/set secific entry, * for QP use RDMA_NLDEV_ATTR_RES_LQPN / RDMA_NLDEV_ATTR_RES_PDN, / u32 / RDMA_NLDEV_ATTR_RES_CQN, / u32 / RDMA_NLDEV_ATTR_RES_MRN, / u32 / RDMA_NLDEV_ATTR_RES_CM_IDN, / u32 / RDMA_NLDEV_ATTR_RES_CTXN, / u32 / / * Identifies the rdma driver. eg: "rxe" or "siw" / RDMA_NLDEV_ATTR_LINK_TYPE, / string / / * net namespace mode for rdma subsystem: * either shared or exclusive among multiple net namespaces. / RDMA_NLDEV_SYS_ATTR_NETNS_MODE, / u8 / / * Device protocol, e.g. ib, iw, usnic, roce and opa / RDMA_NLDEV_ATTR_DEV_PROTOCOL, / string / / * File descriptor handle of the net namespace object / RDMA_NLDEV_NET_NS_FD, / u32 / / * Information about a chardev. * CHARDEV_TYPE is the name of the chardev ABI (ie uverbs, umad, etc) * CHARDEV_ABI signals the ABI revision (historical) * CHARDEV_NAME is the kernel name for the /dev/ file (no directory) * CHARDEV is the 64 bit dev_t for the inode / RDMA_NLDEV_ATTR_CHARDEV_TYPE, / string / RDMA_NLDEV_ATTR_CHARDEV_NAME, / string / RDMA_NLDEV_ATTR_CHARDEV_ABI, / u64 / RDMA_NLDEV_ATTR_CHARDEV, / u64 / RDMA_NLDEV_ATTR_UVERBS_DRIVER_ID, / u64 / / * Counter-specific attributes. / RDMA_NLDEV_ATTR_STAT_MODE, / u32 / RDMA_NLDEV_ATTR_STAT_RES, / u32 / RDMA_NLDEV_ATTR_STAT_AUTO_MODE_MASK, / u32 / RDMA_NLDEV_ATTR_STAT_COUNTER, / nested table / RDMA_NLDEV_ATTR_STAT_COUNTER_ENTRY, / nested table / RDMA_NLDEV_ATTR_STAT_COUNTER_ID, / u32 / RDMA_NLDEV_ATTR_STAT_HWCOUNTERS, / nested table / RDMA_NLDEV_ATTR_STAT_HWCOUNTER_ENTRY, / nested table / RDMA_NLDEV_ATTR_STAT_HWCOUNTER_ENTRY_NAME, / string / RDMA_NLDEV_ATTR_STAT_HWCOUNTER_ENTRY_VALUE, / u64 / / * CQ adaptive moderatio (DIM) / RDMA_NLDEV_ATTR_DEV_DIM, / u8 / RDMA_NLDEV_ATTR_RES_RAW, / binary / RDMA_NLDEV_ATTR_RES_CTX, / nested table / RDMA_NLDEV_ATTR_RES_CTX_ENTRY, / nested table / RDMA_NLDEV_ATTR_RES_SRQ, / nested table / RDMA_NLDEV_ATTR_RES_SRQ_ENTRY, / nested table / RDMA_NLDEV_ATTR_RES_SRQN, / u32 / RDMA_NLDEV_ATTR_MIN_RANGE, / u32 / RDMA_NLDEV_ATTR_MAX_RANGE, / u32 / RDMA_NLDEV_SYS_ATTR_COPY_ON_FORK, / u8 / RDMA_NLDEV_ATTR_STAT_HWCOUNTER_INDEX, / u32 / RDMA_NLDEV_ATTR_STAT_HWCOUNTER_DYNAMIC, / u8 / RDMA_NLDEV_SYS_ATTR_PRIVILEGED_QKEY_MODE, / u8 / RDMA_NLDEV_ATTR_DRIVER_DETAILS, / u8 / / * QP subtype string, used for driver QPs / RDMA_NLDEV_ATTR_RES_SUBTYPE, / string / RDMA_NLDEV_ATTR_DEV_TYPE, / u8 / RDMA_NLDEV_ATTR_PARENT_NAME, / string / RDMA_NLDEV_ATTR_NAME_ASSIGN_TYPE, / u8 / RDMA_NLDEV_ATTR_EVENT_TYPE, / u8 / RDMA_NLDEV_SYS_ATTR_MONITOR_MODE, / u8 / RDMA_NLDEV_ATTR_STAT_OPCOUNTER_ENABLED, / u8 / / * Always the end / RDMA_NLDEV_ATTR_MAX }; / * Supported counter bind modes. All modes are mutual-exclusive. / enum rdma_nl_counter_mode { RDMA_COUNTER_MODE_NONE, / * A qp is bound with a counter automatically during initialization * based on the auto mode (e.g., qp type, ...) / RDMA_COUNTER_MODE_AUTO, / * Which qp are bound with which counter is explicitly specified * by the user / RDMA_COUNTER_MODE_MANUAL, / * Always the end / RDMA_COUNTER_MODE_MAX, }; / * Supported criteria in counter auto mode. * Currently only "qp type" is supported / enum rdma_nl_counter_mask { RDMA_COUNTER_MASK_QP_TYPE = 1, RDMA_COUNTER_MASK_PID = 1 << 1, }; / Supported rdma device types. / enum rdma_nl_dev_type { RDMA_DEVICE_TYPE_SMI = 1, }; / RDMA device name assignment types / enum rdma_nl_name_assign_type { RDMA_NAME_ASSIGN_TYPE_UNKNOWN = 0, RDMA_NAME_ASSIGN_TYPE_USER = 1, / Provided by user-space / }; / * Supported rdma monitoring event types. / enum rdma_nl_notify_event_type { RDMA_REGISTER_EVENT, RDMA_UNREGISTER_EVENT, RDMA_NETDEV_ATTACH_EVENT, RDMA_NETDEV_DETACH_EVENT, RDMA_RENAME_EVENT, RDMA_NETDEV_RENAME_EVENT, }; #endif / _RDMA_NETLINK_H */	15.7 KB	2026-03-24 10:01
📄 rdma_user_cm.h /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) / / * Copyright (c) 2005-2006 Intel Corporation. All rights reserved. * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU * General Public License (GPL) Version 2, available from the file * COPYING in the main directory of this source tree, or the * OpenIB.org BSD license below: * * Redistribution and use in source and binary forms, with or * without modification, are permitted provided that the following * conditions are met: * * - Redistributions of source code must retain the above * copyright notice, this list of conditions and the following * disclaimer. * * - Redistributions in binary form must reproduce the above * copyright notice, this list of conditions and the following * disclaimer in the documentation and/or other materials * provided with the distribution. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. / #ifndef RDMA_USER_CM_H #define RDMA_USER_CM_H #include <linux/types.h> #include <linux/socket.h> #include <linux/in6.h> #include <rdma/ib_user_verbs.h> #include <rdma/ib_user_sa.h> #define RDMA_USER_CM_ABI_VERSION 4 #define RDMA_MAX_PRIVATE_DATA 256 enum { RDMA_USER_CM_CMD_CREATE_ID, RDMA_USER_CM_CMD_DESTROY_ID, RDMA_USER_CM_CMD_BIND_IP, RDMA_USER_CM_CMD_RESOLVE_IP, RDMA_USER_CM_CMD_RESOLVE_ROUTE, RDMA_USER_CM_CMD_QUERY_ROUTE, RDMA_USER_CM_CMD_CONNECT, RDMA_USER_CM_CMD_LISTEN, RDMA_USER_CM_CMD_ACCEPT, RDMA_USER_CM_CMD_REJECT, RDMA_USER_CM_CMD_DISCONNECT, RDMA_USER_CM_CMD_INIT_QP_ATTR, RDMA_USER_CM_CMD_GET_EVENT, RDMA_USER_CM_CMD_GET_OPTION, RDMA_USER_CM_CMD_SET_OPTION, RDMA_USER_CM_CMD_NOTIFY, RDMA_USER_CM_CMD_JOIN_IP_MCAST, RDMA_USER_CM_CMD_LEAVE_MCAST, RDMA_USER_CM_CMD_MIGRATE_ID, RDMA_USER_CM_CMD_QUERY, RDMA_USER_CM_CMD_BIND, RDMA_USER_CM_CMD_RESOLVE_ADDR, RDMA_USER_CM_CMD_JOIN_MCAST }; / See IBTA Annex A11, servies ID bytes 4 & 5 / enum rdma_ucm_port_space { RDMA_PS_IPOIB = 0x0002, RDMA_PS_IB = 0x013F, RDMA_PS_TCP = 0x0106, RDMA_PS_UDP = 0x0111, }; / * command ABI structures. / struct rdma_ucm_cmd_hdr { __u32 cmd; __u16 in; __u16 out; }; struct rdma_ucm_create_id { __aligned_u64 uid; __aligned_u64 response; __u16 ps; / use enum rdma_ucm_port_space / __u8 qp_type; __u8 reserved[5]; }; struct rdma_ucm_create_id_resp { __u32 id; }; struct rdma_ucm_destroy_id { __aligned_u64 response; __u32 id; __u32 reserved; }; struct rdma_ucm_destroy_id_resp { __u32 events_reported; }; struct rdma_ucm_bind_ip { __aligned_u64 response; struct sockaddr_in6 addr; __u32 id; }; struct rdma_ucm_bind { __u32 id; __u16 addr_size; __u16 reserved; struct __kernel_sockaddr_storage addr; }; struct rdma_ucm_resolve_ip { struct sockaddr_in6 src_addr; struct sockaddr_in6 dst_addr; __u32 id; __u32 timeout_ms; }; struct rdma_ucm_resolve_addr { __u32 id; __u32 timeout_ms; __u16 src_size; __u16 dst_size; __u32 reserved; struct __kernel_sockaddr_storage src_addr; struct __kernel_sockaddr_storage dst_addr; }; struct rdma_ucm_resolve_route { __u32 id; __u32 timeout_ms; }; enum { RDMA_USER_CM_QUERY_ADDR, RDMA_USER_CM_QUERY_PATH, RDMA_USER_CM_QUERY_GID }; struct rdma_ucm_query { __aligned_u64 response; __u32 id; __u32 option; }; struct rdma_ucm_query_route_resp { __aligned_u64 node_guid; struct ib_user_path_rec ib_route[2]; struct sockaddr_in6 src_addr; struct sockaddr_in6 dst_addr; __u32 num_paths; __u8 port_num; __u8 reserved[3]; __u32 ibdev_index; __u32 reserved1; }; struct rdma_ucm_query_addr_resp { __aligned_u64 node_guid; __u8 port_num; __u8 reserved; __u16 pkey; __u16 src_size; __u16 dst_size; struct __kernel_sockaddr_storage src_addr; struct __kernel_sockaddr_storage dst_addr; __u32 ibdev_index; __u32 reserved1; }; struct rdma_ucm_query_path_resp { __u32 num_paths; __u32 reserved; struct ib_path_rec_data path_data[]; }; struct rdma_ucm_conn_param { __u32 qp_num; __u32 qkey; __u8 private_data[RDMA_MAX_PRIVATE_DATA]; __u8 private_data_len; __u8 srq; __u8 responder_resources; __u8 initiator_depth; __u8 flow_control; __u8 retry_count; __u8 rnr_retry_count; __u8 valid; }; struct rdma_ucm_ud_param { __u32 qp_num; __u32 qkey; struct ib_uverbs_ah_attr ah_attr; __u8 private_data[RDMA_MAX_PRIVATE_DATA]; __u8 private_data_len; __u8 reserved[7]; }; struct rdma_ucm_ece { __u32 vendor_id; __u32 attr_mod; }; struct rdma_ucm_connect { struct rdma_ucm_conn_param conn_param; __u32 id; __u32 reserved; struct rdma_ucm_ece ece; }; struct rdma_ucm_listen { __u32 id; __u32 backlog; }; struct rdma_ucm_accept { __aligned_u64 uid; struct rdma_ucm_conn_param conn_param; __u32 id; __u32 reserved; struct rdma_ucm_ece ece; }; struct rdma_ucm_reject { __u32 id; __u8 private_data_len; __u8 reason; __u8 reserved[2]; __u8 private_data[RDMA_MAX_PRIVATE_DATA]; }; struct rdma_ucm_disconnect { __u32 id; }; struct rdma_ucm_init_qp_attr { __aligned_u64 response; __u32 id; __u32 qp_state; }; struct rdma_ucm_notify { __u32 id; __u32 event; }; struct rdma_ucm_join_ip_mcast { __aligned_u64 response; / rdma_ucm_create_id_resp / __aligned_u64 uid; struct sockaddr_in6 addr; __u32 id; }; / Multicast join flags / enum { RDMA_MC_JOIN_FLAG_FULLMEMBER, RDMA_MC_JOIN_FLAG_SENDONLY_FULLMEMBER, RDMA_MC_JOIN_FLAG_RESERVED, }; struct rdma_ucm_join_mcast { __aligned_u64 response; / rdma_ucma_create_id_resp / __aligned_u64 uid; __u32 id; __u16 addr_size; __u16 join_flags; struct __kernel_sockaddr_storage addr; }; struct rdma_ucm_get_event { __aligned_u64 response; }; struct rdma_ucm_event_resp { __aligned_u64 uid; __u32 id; __u32 event; __u32 status; / * NOTE: This union is not aligned to 8 bytes so none of the union * members may contain a u64 or anything with higher alignment than 4. / union { struct rdma_ucm_conn_param conn; struct rdma_ucm_ud_param ud; } param; __u32 reserved; struct rdma_ucm_ece ece; }; / Option levels / enum { RDMA_OPTION_ID = 0, RDMA_OPTION_IB = 1 }; / Option details / enum { RDMA_OPTION_ID_TOS = 0, RDMA_OPTION_ID_REUSEADDR = 1, RDMA_OPTION_ID_AFONLY = 2, RDMA_OPTION_ID_ACK_TIMEOUT = 3 }; enum { RDMA_OPTION_IB_PATH = 1 }; struct rdma_ucm_set_option { __aligned_u64 optval; __u32 id; __u32 level; __u32 optname; __u32 optlen; }; struct rdma_ucm_migrate_id { __aligned_u64 response; __u32 id; __u32 fd; }; struct rdma_ucm_migrate_resp { __u32 events_reported; }; #endif / RDMA_USER_CM_H */	6.96 KB	2026-03-24 10:01
📄 rdma_user_ioctl.h /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) / / * Copyright (c) 2016 Mellanox Technologies, LTD. All rights reserved. * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU * General Public License (GPL) Version 2, available from the file * COPYING in the main directory of this source tree, or the * OpenIB.org BSD license below: * * Redistribution and use in source and binary forms, with or * without modification, are permitted provided that the following * conditions are met: * * - Redistributions of source code must retain the above * copyright notice, this list of conditions and the following * disclaimer. * * - Redistributions in binary form must reproduce the above * copyright notice, this list of conditions and the following * disclaimer in the documentation and/or other materials * provided with the distribution. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. / #ifndef RDMA_USER_IOCTL_H #define RDMA_USER_IOCTL_H #include <rdma/ib_user_mad.h> #include <rdma/hfi/hfi1_ioctl.h> #include <rdma/rdma_user_ioctl_cmds.h> / Legacy name, for user space application which already use it / #define IB_IOCTL_MAGIC RDMA_IOCTL_MAGIC / * General blocks assignments * It is closed on purpose - do not expose it to user space * #define MAD_CMD_BASE 0x00 * #define HFI1_CMD_BAS 0xE0 / / MAD specific section / #define IB_USER_MAD_REGISTER_AGENT _IOWR(RDMA_IOCTL_MAGIC, 0x01, struct ib_user_mad_reg_req) #define IB_USER_MAD_UNREGISTER_AGENT _IOW(RDMA_IOCTL_MAGIC, 0x02, __u32) #define IB_USER_MAD_ENABLE_PKEY _IO(RDMA_IOCTL_MAGIC, 0x03) #define IB_USER_MAD_REGISTER_AGENT2 _IOWR(RDMA_IOCTL_MAGIC, 0x04, struct ib_user_mad_reg_req2) / HFI specific section / / allocate HFI and context / #define HFI1_IOCTL_ASSIGN_CTXT _IOWR(RDMA_IOCTL_MAGIC, 0xE1, struct hfi1_user_info) / find out what resources we got / #define HFI1_IOCTL_CTXT_INFO _IOW(RDMA_IOCTL_MAGIC, 0xE2, struct hfi1_ctxt_info) / set up userspace / #define HFI1_IOCTL_USER_INFO _IOW(RDMA_IOCTL_MAGIC, 0xE3, struct hfi1_base_info) / update expected TID entries / #define HFI1_IOCTL_TID_UPDATE _IOWR(RDMA_IOCTL_MAGIC, 0xE4, struct hfi1_tid_info) / free expected TID entries / #define HFI1_IOCTL_TID_FREE _IOWR(RDMA_IOCTL_MAGIC, 0xE5, struct hfi1_tid_info) / force an update of PIO credit / #define HFI1_IOCTL_CREDIT_UPD _IO(RDMA_IOCTL_MAGIC, 0xE6) / control receipt of packets / #define HFI1_IOCTL_RECV_CTRL _IOW(RDMA_IOCTL_MAGIC, 0xE8, int) / set the kind of polling we want / #define HFI1_IOCTL_POLL_TYPE _IOW(RDMA_IOCTL_MAGIC, 0xE9, int) / ack & clear user status bits / #define HFI1_IOCTL_ACK_EVENT _IOW(RDMA_IOCTL_MAGIC, 0xEA, unsigned long) / set context's pkey / #define HFI1_IOCTL_SET_PKEY _IOW(RDMA_IOCTL_MAGIC, 0xEB, __u16) / reset context's HW send context / #define HFI1_IOCTL_CTXT_RESET _IO(RDMA_IOCTL_MAGIC, 0xEC) / read TID cache invalidations / #define HFI1_IOCTL_TID_INVAL_READ _IOWR(RDMA_IOCTL_MAGIC, 0xED, struct hfi1_tid_info) / get the version of the user cdev / #define HFI1_IOCTL_GET_VERS _IOR(RDMA_IOCTL_MAGIC, 0xEE, int) #endif / RDMA_USER_IOCTL_H */	3.66 KB	2026-03-24 10:01
📄 rdma_user_ioctl_cmds.h /* * Copyright (c) 2018, Mellanox Technologies inc. All rights reserved. * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU * General Public License (GPL) Version 2, available from the file * COPYING in the main directory of this source tree, or the * OpenIB.org BSD license below: * * Redistribution and use in source and binary forms, with or * without modification, are permitted provided that the following * conditions are met: * * - Redistributions of source code must retain the above * copyright notice, this list of conditions and the following * disclaimer. * * - Redistributions in binary form must reproduce the above * copyright notice, this list of conditions and the following * disclaimer in the documentation and/or other materials * provided with the distribution. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. / #ifndef RDMA_USER_IOCTL_CMDS_H #define RDMA_USER_IOCTL_CMDS_H #include <linux/types.h> #include <linux/ioctl.h> / Documentation/userspace-api/ioctl/ioctl-number.rst / #define RDMA_IOCTL_MAGIC 0x1b #define RDMA_VERBS_IOCTL \ _IOWR(RDMA_IOCTL_MAGIC, 1, struct ib_uverbs_ioctl_hdr) enum { / User input / UVERBS_ATTR_F_MANDATORY = 1U << 0, / * Valid output bit should be ignored and considered set in * mandatory fields. This bit is kernel output. / UVERBS_ATTR_F_VALID_OUTPUT = 1U << 1, }; struct ib_uverbs_attr { __u16 attr_id; / command specific type attribute / __u16 len; / only for pointers and IDRs array / __u16 flags; / combination of UVERBS_ATTR_F_XXXX / union { struct { __u8 elem_id; __u8 reserved; } enum_data; __u16 reserved; } attr_data; union { / * ptr to command, __inline__ data, idr/fd or * ptr to __u32 array of IDRs / __aligned_u64 data; / Used by FD_IN and FD_OUT */ __s64 data_s64; }; }; struct ib_uverbs_ioctl_hdr { __u16 length; __u16 object_id; __u16 method_id; __u16 num_attrs; __aligned_u64 reserved1; __u32 driver_id; __u32 reserved2; struct ib_uverbs_attr attrs[]; }; #endif	2.56 KB	2026-03-24 10:01
📄 rdma_user_rxe.h /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) / / * Copyright (c) 2016 Mellanox Technologies Ltd. All rights reserved. * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU * General Public License (GPL) Version 2, available from the file * COPYING in the main directory of this source tree, or the * OpenIB.org BSD license below: * * Redistribution and use in source and binary forms, with or * without modification, are permitted provided that the following * conditions are met: * * - Redistributions of source code must retain the above * copyright notice, this list of conditions and the following * disclaimer. * * - Redistributions in binary form must reproduce the above * copyright notice, this list of conditions and the following * disclaimer in the documentation and/or other materials * provided with the distribution. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. / #ifndef RDMA_USER_RXE_H #define RDMA_USER_RXE_H #include <linux/types.h> #include <linux/socket.h> #include <linux/in.h> #include <linux/in6.h> enum { RXE_NETWORK_TYPE_IPV4 = 1, RXE_NETWORK_TYPE_IPV6 = 2, }; union rxe_gid { __u8 raw[16]; struct { __be64 subnet_prefix; __be64 interface_id; } global; }; struct rxe_global_route { union rxe_gid dgid; __u32 flow_label; __u8 sgid_index; __u8 hop_limit; __u8 traffic_class; }; struct rxe_av { __u8 port_num; / From RXE_NETWORK_TYPE_* / __u8 network_type; __u8 dmac[6]; struct rxe_global_route grh; union { struct sockaddr_in _sockaddr_in; struct sockaddr_in6 _sockaddr_in6; } sgid_addr, dgid_addr; }; struct rxe_send_wr { __aligned_u64 wr_id; __u32 reserved; __u32 opcode; __u32 send_flags; union { __be32 imm_data; __u32 invalidate_rkey; } ex; union { struct { __aligned_u64 remote_addr; __u32 length; __u32 rkey; __u8 type; __u8 level; } flush; struct { __aligned_u64 remote_addr; __u32 rkey; __u32 reserved; } rdma; struct { __aligned_u64 remote_addr; __aligned_u64 compare_add; __aligned_u64 swap; __u32 rkey; __u32 reserved; } atomic; struct { __u32 remote_qpn; __u32 remote_qkey; __u16 pkey_index; __u16 reserved; __u32 ah_num; __u32 pad[4]; struct rxe_av av; } ud; struct { __aligned_u64 addr; __aligned_u64 length; __u32 mr_lkey; __u32 mw_rkey; __u32 rkey; __u32 access; } mw; / reg is only used by the kernel and is not part of the uapi / } wr; }; struct rxe_sge { __aligned_u64 addr; __u32 length; __u32 lkey; }; struct mminfo { __aligned_u64 offset; __u32 size; __u32 pad; }; struct rxe_dma_info { __u32 length; __u32 resid; __u32 cur_sge; __u32 num_sge; __u32 sge_offset; __u32 reserved; union { __DECLARE_FLEX_ARRAY(__u8, inline_data); __DECLARE_FLEX_ARRAY(__u8, atomic_wr); __DECLARE_FLEX_ARRAY(struct rxe_sge, sge); }; }; struct rxe_send_wqe { struct rxe_send_wr wr; __u32 status; __u32 state; __aligned_u64 iova; __u32 mask; __u32 first_psn; __u32 last_psn; __u32 ack_length; __u32 ssn; __u32 has_rd_atomic; struct rxe_dma_info dma; }; struct rxe_recv_wqe { __aligned_u64 wr_id; __u32 reserved; __u32 padding; struct rxe_dma_info dma; }; struct rxe_create_ah_resp { __u32 ah_num; __u32 reserved; }; struct rxe_create_cq_resp { struct mminfo mi; }; struct rxe_resize_cq_resp { struct mminfo mi; }; struct rxe_create_qp_resp { struct mminfo rq_mi; struct mminfo sq_mi; }; struct rxe_create_srq_resp { struct mminfo mi; __u32 srq_num; __u32 reserved; }; struct rxe_modify_srq_cmd { __aligned_u64 mmap_info_addr; }; / This data structure is stored at the base of work and * completion queues shared between user space and kernel space. * It contains the producer and consumer indices. Is also * contains a copy of the queue size parameters for user space * to use but the kernel must use the parameters in the * rxe_queue struct. For performance reasons arrange to have * producer and consumer indices in separate cache lines * the kernel should always mask the indices to avoid accessing * memory outside of the data area / struct rxe_queue_buf { __u32 log2_elem_size; __u32 index_mask; __u32 pad_1[30]; __u32 producer_index; __u32 pad_2[31]; __u32 consumer_index; __u32 pad_3[31]; __u8 data[]; }; #endif / RDMA_USER_RXE_H */	4.86 KB	2026-03-24 10:01
📄 rvt-abi.h /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) / / * This file contains defines, structures, etc. that are used * to communicate between kernel and user code. / #ifndef RVT_ABI_USER_H #define RVT_ABI_USER_H #include <linux/types.h> #include <rdma/ib_user_verbs.h> #ifndef RDMA_ATOMIC_UAPI #define RDMA_ATOMIC_UAPI(_type, _name) struct{ _type val; } _name #endif struct rvt_wqe_sge { __aligned_u64 addr; __u32 length; __u32 lkey; }; / * This structure is used to contain the head pointer, tail pointer, * and completion queue entries as a single memory allocation so * it can be mmap'ed into user space. / struct rvt_cq_wc { / index of next entry to fill / RDMA_ATOMIC_UAPI(__u32, head); / index of next ib_poll_cq() entry / RDMA_ATOMIC_UAPI(__u32, tail); / these are actually size ibcq.cqe + 1 / struct ib_uverbs_wc uqueue[]; }; / * Receive work request queue entry. * The size of the sg_list is determined when the QP (or SRQ) is created * and stored in qp->r_rq.max_sge (or srq->rq.max_sge). / struct rvt_rwqe { __u64 wr_id; __u8 num_sge; __u8 padding[7]; struct rvt_wqe_sge sg_list[]; }; / * This structure is used to contain the head pointer, tail pointer, * and receive work queue entries as a single memory allocation so * it can be mmap'ed into user space. * Note that the wq array elements are variable size so you can't * just index into the array to get the N'th element; * use get_rwqe_ptr() for user space and rvt_get_rwqe_ptr() * for kernel space. / struct rvt_rwq { / new work requests posted to the head / RDMA_ATOMIC_UAPI(__u32, head); / receives pull requests from here. / RDMA_ATOMIC_UAPI(__u32, tail); struct rvt_rwqe wq[]; }; #endif / RVT_ABI_USER_H */	1.73 KB	2026-03-24 10:01
📄 siw-abi.h /* SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause / / Authors: Bernard Metzler <bmt@zurich.ibm.com> / / Copyright (c) 2008-2019, IBM Corporation / #ifndef _SIW_USER_H #define _SIW_USER_H #include <linux/types.h> #define SIW_NODE_DESC_COMMON "Software iWARP stack" #define SIW_ABI_VERSION 1 #define SIW_MAX_SGE 6 #define SIW_UOBJ_MAX_KEY 0x08FFFF #define SIW_INVAL_UOBJ_KEY (SIW_UOBJ_MAX_KEY + 1) struct siw_uresp_create_cq { __u32 cq_id; __u32 num_cqe; __aligned_u64 cq_key; }; struct siw_uresp_create_qp { __u32 qp_id; __u32 num_sqe; __u32 num_rqe; __u32 pad; __aligned_u64 sq_key; __aligned_u64 rq_key; }; struct siw_ureq_reg_mr { __u8 stag_key; __u8 reserved[3]; __u32 pad; }; struct siw_uresp_reg_mr { __u32 stag; __u32 pad; }; struct siw_uresp_create_srq { __u32 num_rqe; __u32 pad; __aligned_u64 srq_key; }; struct siw_uresp_alloc_ctx { __u32 dev_id; __u32 pad; }; enum siw_opcode { SIW_OP_WRITE, SIW_OP_READ, SIW_OP_READ_LOCAL_INV, SIW_OP_SEND, SIW_OP_SEND_WITH_IMM, SIW_OP_SEND_REMOTE_INV, / Unsupported / SIW_OP_FETCH_AND_ADD, SIW_OP_COMP_AND_SWAP, SIW_OP_RECEIVE, / provider internal SQE / SIW_OP_READ_RESPONSE, / * below opcodes valid for * in-kernel clients only / SIW_OP_INVAL_STAG, SIW_OP_REG_MR, SIW_NUM_OPCODES }; / Keep it same as ibv_sge to allow for memcpy / struct siw_sge { __aligned_u64 laddr; __u32 length; __u32 lkey; }; / * Inline data are kept within the work request itself occupying * the space of sge[1] .. sge[n]. Therefore, __inline__ data cannot be * supported if SIW_MAX_SGE is below 2 elements. / #define SIW_MAX_INLINE (sizeof(struct siw_sge) (SIW_MAX_SGE - 1)) #if SIW_MAX_SGE < 2 #error "SIW_MAX_SGE must be at least 2" #endif enum siw_wqe_flags { SIW_WQE_VALID = 1, SIW_WQE_INLINE = (1 << 1), SIW_WQE_SIGNALLED = (1 << 2), SIW_WQE_SOLICITED = (1 << 3), SIW_WQE_READ_FENCE = (1 << 4), SIW_WQE_REM_INVAL = (1 << 5), SIW_WQE_COMPLETED = (1 << 6) }; /* Send Queue Element / struct siw_sqe { __aligned_u64 id; __u16 flags; __u8 num_sge; / Contains enum siw_opcode values / __u8 opcode; __u32 rkey; union { __aligned_u64 raddr; __aligned_u64 base_mr; }; union { struct siw_sge sge[SIW_MAX_SGE]; __aligned_u64 access; }; }; / Receive Queue Element / struct siw_rqe { __aligned_u64 id; __u16 flags; __u8 num_sge; / * only used by kernel driver, * ignored if set by user / __u8 opcode; __u32 unused; struct siw_sge sge[SIW_MAX_SGE]; }; enum siw_notify_flags { SIW_NOTIFY_NOT = (0), SIW_NOTIFY_SOLICITED = (1 << 0), SIW_NOTIFY_NEXT_COMPLETION = (1 << 1), SIW_NOTIFY_MISSED_EVENTS = (1 << 2), SIW_NOTIFY_ALL = SIW_NOTIFY_SOLICITED \| SIW_NOTIFY_NEXT_COMPLETION \| SIW_NOTIFY_MISSED_EVENTS }; enum siw_wc_status { SIW_WC_SUCCESS, SIW_WC_LOC_LEN_ERR, SIW_WC_LOC_PROT_ERR, SIW_WC_LOC_QP_OP_ERR, SIW_WC_WR_FLUSH_ERR, SIW_WC_BAD_RESP_ERR, SIW_WC_LOC_ACCESS_ERR, SIW_WC_REM_ACCESS_ERR, SIW_WC_REM_INV_REQ_ERR, SIW_WC_GENERAL_ERR, SIW_NUM_WC_STATUS }; struct siw_cqe { __aligned_u64 id; __u8 flags; __u8 opcode; __u16 status; __u32 bytes; union { __aligned_u64 imm_data; __u32 inval_stag; }; / QP number or QP pointer / union { struct ib_qp base_qp; __aligned_u64 qp_id; }; }; /* * Shared structure between user and kernel * to control CQ arming. */ struct siw_cq_ctrl { __u32 flags; __u32 pad; }; #endif	3.35 KB	2026-03-24 10:01
📄 vmw_pvrdma-abi.h /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) / / * Copyright (c) 2012-2016 VMware, Inc. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of EITHER the GNU General Public License * version 2 as published by the Free Software Foundation or the BSD * 2-Clause License. This program is distributed in the hope that it * will be useful, but WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License version 2 for more details at * http://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html. * * You should have received a copy of the GNU General Public License * along with this program available in the file COPYING in the main * directory of this source tree. * * The BSD 2-Clause License * * Redistribution and use in source and binary forms, with or * without modification, are permitted provided that the following * conditions are met: * * - Redistributions of source code must retain the above * copyright notice, this list of conditions and the following * disclaimer. * * - Redistributions in binary form must reproduce the above * copyright notice, this list of conditions and the following * disclaimer in the documentation and/or other materials * provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. / #ifndef __VMW_PVRDMA_ABI_H__ #define __VMW_PVRDMA_ABI_H__ #include <linux/types.h> #define PVRDMA_UVERBS_ABI_VERSION 3 / ABI Version. / #define PVRDMA_UAR_HANDLE_MASK 0x00FFFFFF / Bottom 24 bits. / #define PVRDMA_UAR_QP_OFFSET 0 / QP doorbell. / #define PVRDMA_UAR_QP_SEND (1 << 30) / Send bit. / #define PVRDMA_UAR_QP_RECV (1 << 31) / Recv bit. / #define PVRDMA_UAR_CQ_OFFSET 4 / CQ doorbell. / #define PVRDMA_UAR_CQ_ARM_SOL (1 << 29) / Arm solicited bit. / #define PVRDMA_UAR_CQ_ARM (1 << 30) / Arm bit. / #define PVRDMA_UAR_CQ_POLL (1 << 31) / Poll bit. / #define PVRDMA_UAR_SRQ_OFFSET 8 / SRQ doorbell. / #define PVRDMA_UAR_SRQ_RECV (1 << 30) / Recv bit. / enum pvrdma_wr_opcode { PVRDMA_WR_RDMA_WRITE, PVRDMA_WR_RDMA_WRITE_WITH_IMM, PVRDMA_WR_SEND, PVRDMA_WR_SEND_WITH_IMM, PVRDMA_WR_RDMA_READ, PVRDMA_WR_ATOMIC_CMP_AND_SWP, PVRDMA_WR_ATOMIC_FETCH_AND_ADD, PVRDMA_WR_LSO, PVRDMA_WR_SEND_WITH_INV, PVRDMA_WR_RDMA_READ_WITH_INV, PVRDMA_WR_LOCAL_INV, PVRDMA_WR_FAST_REG_MR, PVRDMA_WR_MASKED_ATOMIC_CMP_AND_SWP, PVRDMA_WR_MASKED_ATOMIC_FETCH_AND_ADD, PVRDMA_WR_BIND_MW, PVRDMA_WR_REG_SIG_MR, PVRDMA_WR_ERROR, }; enum pvrdma_wc_status { PVRDMA_WC_SUCCESS, PVRDMA_WC_LOC_LEN_ERR, PVRDMA_WC_LOC_QP_OP_ERR, PVRDMA_WC_LOC_EEC_OP_ERR, PVRDMA_WC_LOC_PROT_ERR, PVRDMA_WC_WR_FLUSH_ERR, PVRDMA_WC_MW_BIND_ERR, PVRDMA_WC_BAD_RESP_ERR, PVRDMA_WC_LOC_ACCESS_ERR, PVRDMA_WC_REM_INV_REQ_ERR, PVRDMA_WC_REM_ACCESS_ERR, PVRDMA_WC_REM_OP_ERR, PVRDMA_WC_RETRY_EXC_ERR, PVRDMA_WC_RNR_RETRY_EXC_ERR, PVRDMA_WC_LOC_RDD_VIOL_ERR, PVRDMA_WC_REM_INV_RD_REQ_ERR, PVRDMA_WC_REM_ABORT_ERR, PVRDMA_WC_INV_EECN_ERR, PVRDMA_WC_INV_EEC_STATE_ERR, PVRDMA_WC_FATAL_ERR, PVRDMA_WC_RESP_TIMEOUT_ERR, PVRDMA_WC_GENERAL_ERR, }; enum pvrdma_wc_opcode { PVRDMA_WC_SEND, PVRDMA_WC_RDMA_WRITE, PVRDMA_WC_RDMA_READ, PVRDMA_WC_COMP_SWAP, PVRDMA_WC_FETCH_ADD, PVRDMA_WC_BIND_MW, PVRDMA_WC_LSO, PVRDMA_WC_LOCAL_INV, PVRDMA_WC_FAST_REG_MR, PVRDMA_WC_MASKED_COMP_SWAP, PVRDMA_WC_MASKED_FETCH_ADD, PVRDMA_WC_RECV = 1 << 7, PVRDMA_WC_RECV_RDMA_WITH_IMM, }; enum pvrdma_wc_flags { PVRDMA_WC_GRH = 1 << 0, PVRDMA_WC_WITH_IMM = 1 << 1, PVRDMA_WC_WITH_INVALIDATE = 1 << 2, PVRDMA_WC_IP_CSUM_OK = 1 << 3, PVRDMA_WC_WITH_SMAC = 1 << 4, PVRDMA_WC_WITH_VLAN = 1 << 5, PVRDMA_WC_WITH_NETWORK_HDR_TYPE = 1 << 6, PVRDMA_WC_FLAGS_MAX = PVRDMA_WC_WITH_NETWORK_HDR_TYPE, }; enum pvrdma_network_type { PVRDMA_NETWORK_IB, PVRDMA_NETWORK_ROCE_V1 = PVRDMA_NETWORK_IB, PVRDMA_NETWORK_IPV4, PVRDMA_NETWORK_IPV6 }; struct pvrdma_alloc_ucontext_resp { __u32 qp_tab_size; __u32 reserved; }; struct pvrdma_alloc_pd_resp { __u32 pdn; __u32 reserved; }; struct pvrdma_create_cq { __aligned_u64 buf_addr; __u32 buf_size; __u32 reserved; }; struct pvrdma_create_cq_resp { __u32 cqn; __u32 reserved; }; struct pvrdma_resize_cq { __aligned_u64 buf_addr; __u32 buf_size; __u32 reserved; }; struct pvrdma_create_srq { __aligned_u64 buf_addr; __u32 buf_size; __u32 reserved; }; struct pvrdma_create_srq_resp { __u32 srqn; __u32 reserved; }; struct pvrdma_create_qp { __aligned_u64 rbuf_addr; __aligned_u64 sbuf_addr; __u32 rbuf_size; __u32 sbuf_size; __aligned_u64 qp_addr; }; struct pvrdma_create_qp_resp { __u32 qpn; __u32 qp_handle; }; / PVRDMA masked atomic compare and swap / struct pvrdma_ex_cmp_swap { __aligned_u64 swap_val; __aligned_u64 compare_val; __aligned_u64 swap_mask; __aligned_u64 compare_mask; }; / PVRDMA masked atomic fetch and add / struct pvrdma_ex_fetch_add { __aligned_u64 add_val; __aligned_u64 field_boundary; }; / PVRDMA address vector. / struct pvrdma_av { __u32 port_pd; __u32 sl_tclass_flowlabel; __u8 dgid[16]; __u8 src_path_bits; __u8 gid_index; __u8 stat_rate; __u8 hop_limit; __u8 dmac[6]; __u8 reserved[6]; }; / PVRDMA scatter/gather entry / struct pvrdma_sge { __aligned_u64 addr; __u32 length; __u32 lkey; }; / PVRDMA receive queue work request / struct pvrdma_rq_wqe_hdr { __aligned_u64 wr_id; / wr id / __u32 num_sge; / size of s/g array / __u32 total_len; / reserved / }; / Use pvrdma_sge (ib_sge) for receive queue s/g array elements. / / PVRDMA send queue work request / struct pvrdma_sq_wqe_hdr { __aligned_u64 wr_id; / wr id / __u32 num_sge; / size of s/g array / __u32 total_len; / reserved / __u32 opcode; / operation type / __u32 send_flags; / wr flags / union { __be32 imm_data; __u32 invalidate_rkey; } ex; __u32 reserved; union { struct { __aligned_u64 remote_addr; __u32 rkey; __u8 reserved[4]; } rdma; struct { __aligned_u64 remote_addr; __aligned_u64 compare_add; __aligned_u64 swap; __u32 rkey; __u32 reserved; } atomic; struct { __aligned_u64 remote_addr; __u32 log_arg_sz; __u32 rkey; union { struct pvrdma_ex_cmp_swap cmp_swap; struct pvrdma_ex_fetch_add fetch_add; } wr_data; } masked_atomics; struct { __aligned_u64 iova_start; __aligned_u64 pl_pdir_dma; __u32 page_shift; __u32 page_list_len; __u32 length; __u32 access_flags; __u32 rkey; __u32 reserved; } fast_reg; struct { __u32 remote_qpn; __u32 remote_qkey; struct pvrdma_av av; } ud; } wr; }; / Use pvrdma_sge (ib_sge) for send queue s/g array elements. / / Completion queue element. / struct pvrdma_cqe { __aligned_u64 wr_id; __aligned_u64 qp; __u32 opcode; __u32 status; __u32 byte_len; __be32 imm_data; __u32 src_qp; __u32 wc_flags; __u32 vendor_err; __u16 pkey_index; __u16 slid; __u8 sl; __u8 dlid_path_bits; __u8 port_num; __u8 smac[6]; __u8 network_hdr_type; __u8 reserved2[6]; / Pad to next power of 2 (64). / }; #endif / __VMW_PVRDMA_ABI_H__ */	7.82 KB	2026-03-24 10:01

Edit File:

Terminal